Makoto Yabuuchi
Orcid: 0000-0003-1515-4726
According to our database1,
Makoto Yabuuchi
authored at least 35 papers
between 2007 and 2024.
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Bibliography
2024
A 3-nm FinFET 27.6-Mbit/mm<sup>2</sup> Single-Port 6T SRAM Enabling 0.48-1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking.
IEEE J. Solid State Circuits, April, 2024
2023
A 3-nm 27.6-Mbit/mm2 Self-timed SRAM Enabling 0.48 - 1.2 V Wide Operating Range with Far-end Pre-charge and Weak-Bit Tracking.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
2021
An Analysis of Local BTI Variation with Ring-Oscillator in Advanced Processes and Its Impact on Logic Circuit and SRAM.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021
2020
A 29.2 Mb/mm<sup>2</sup> Ultra High Density SRAM Macro using 7nm FinFET Technology with Dual-Edge Driven Wordline/Bitline and Write/Read-Assist Circuit.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
A 7nm Fin-FET 4.04-Mb/mm2 TCAM with Improved Electromigration Reliability Using Far-Side Driving Scheme and Self-Adjust Reference Match-Line Amplifier.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2019
A Ternary Based Bit Scalable, 8.80 TOPS/W CNN accelerator with Many-core Processing-in-memory Architecture with 896K synapses/mm<sup>2</sup>.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
Study of Local BTI Variation and its Impact on Logic Circuit and SRAM in 7 nm Fin-FET Process.
Proceedings of the IEEE International Reliability Physics Symposium, 2019
2018
A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures.
IEEE Trans. Very Large Scale Integr. Syst., 2018
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
40-nm 64-kbit Buffer/Backup SRAM with 330 nW Standby Power at 65°C Using 3.3 V IO MOSs for PMIC less MCU in IoT Applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2016
A 6.05-Mb/mm<sup>2</sup> 16-nm FinFET double pumping 1W1R 2-port SRAM with 313 ps read access time.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
A 5.92-Mb/mm<sup>2</sup> 28-nm pseudo 2-read/write dual-port SRAM using double pumping circuitry.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
2015
1.8 Mbit/mm<sup>2</sup> ternary-CAM macro with 484 ps search access time in 16 nm Fin-FET bulk CMOS technology.
Proceedings of the Symposium on VLSI Circuits, 2015
2014
28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique.
IEEE Trans. Very Large Scale Integr. Syst., 2014
A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation.
IEICE Trans. Electron., 2014
A 512-kb 1-GHz 28-nm partially write-assisted dual-port SRAM with self-adjustable negative bias bitline.
Proceedings of the Symposium on VLSI Circuits, 2014
13.3 20nm High-density single-port and dual-port SRAMs with wordline-voltage-adjustment system for read/write assists.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
Assessing uniqueness and reliability of SRAM-based Physical Unclonable Functions from silicon measurements in 45-nm bulk CMOS.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
2013
A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry.
Proceedings of the International Symposium on Quality Electronic Design, 2013
A 28nm high density 1R/1W 8T-SRAM macro with screening circuitry against read disturb failure.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
A stable chip-ID generating physical uncloneable function using random address errors in SRAM.
Proceedings of the IEEE 25th International SOC Conference, 2012
A 28nm 360ps-access-time two-port SRAM with a time-sharing scheme to circumvent read disturbs.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
A Test Screening Method for 28 nm HK/MG Single-Port and Dual-Port SRAMs Considering with Dynamic Stability and Read/Write Disturb Issues.
Proceedings of the 21st IEEE Asian Test Symposium, 2012
2011
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
2010
Dependable SRAM with enhanced read-/write-margins by fine-grained assist bias control for low-voltage operation.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010
A 0.5V 100MHz PD-SOI SRAM with enhanced read stability and write margin by asymmetric MOSFET and forward body bias.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2009
Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access.
IEEE J. Solid State Circuits, 2009
2008
A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die.
IEEE J. Solid State Circuits, 2008
A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations.
IEEE J. Solid State Circuits, 2008
A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues.
IEEE J. Solid State Circuits, 2008
2007
A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits.
IEEE J. Solid State Circuits, 2007
A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007