Jiro Ishikawa

According to our database, Jiro Ishikawa authored at least 4 papers between 2011 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

A Cost Effective Test Screening Circuit for embedded SRAM with Resume Standby on 110-nm SoC/MCU.

Yoshisato Yokoyama, Kenji Goto, Tomohiro Miura, Yukari Ouchi, Daisuke Nakamura, Jiro Ishikawa, Shunya Nagata, Yoshiki Tsujihashi, Yuichiro Ishii

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018

40-nm 64-kbit Buffer/Backup SRAM with 330 nW Standby Power at 65°C Using 3.3 V IO MOSs for PMIC less MCU in IoT Applications.

Yoshisato Yokoyama, Tomohiro Miura, Yukari Ouchi, Daisuke Nakamura, Jiro Ishikawa, Shunya Nagata, Makoto Yabuuchi, Yuichiro Ishii, Koji Nii

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2014

28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique.

Yukiko Umemoto, Koji Nii, Jiro Ishikawa, Makoto Yabuuchi, Kazuyoshi Okamoto, Yasumasa Tsukamoto, Shinji Tanaka, Koji Tanaka, Tetsuya Matsumura, Kazutaka Mori, Kazumasa Yanagisawa

IEEE Trans. Very Large Scale Integr. Syst., 2014

2011

A 28 nm 50% power reduced 2T mask ROM with 0.72 ns read access time using column source bias.

Yukiko Umemoto, Koji Nii, Jiro Ishikawa, Kazuyoshi Okamoto, Kazutaka Mori, Kazumasa Yanagisawa

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011