Min-Seong Choo
Orcid: 0000-0002-8638-6332
According to our database1,
Min-Seong Choo
authored at least 20 papers
between 2015 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2024
Hardware and Software Co-Simulation Methodology for Processing-in-Memory Bitcell application.
Proceedings of the International Conference on Electronics, Information, and Communication, 2024
Analysis of ADC Quantization Effect in Processing-In-Memory Macro in Various Low-Precision Deep Neural Networks.
Proceedings of the International Conference on Electronics, Information, and Communication, 2024
An Analysis of 32-Gb/s and Full-Rate Phase Interpolator based Clock and Data Recovery.
Proceedings of the International Conference on Electronics, Information, and Communication, 2024
2023
An Automated Design Methodology for Ring Voltage-Controlled Oscillators in Nanometer CMOS Technologies.
IEEE Access, 2023
Radiation-Hardened Processing-In-Memory Crossbar Array With Hybrid Synapse Devices for Space Application.
Proceedings of the International Conference on Electronics, Information, and Communication, 2023
Direct Phase Control in Digital Phase-Locked Loop Mitigating Loop Delay Effect inside Digital Filter.
Proceedings of the International Conference on Electronics, Information, and Communication, 2023
2022
A -247.1 dB FoM, -77.9dBc Reference Spur Ring-Oscillator-Based Injection-Locked Clock Multiplier with Multi-Phase-Based Calibration.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
2021
A 4-20-Gb/s 1.87-pJ/b Continuous-Rate Digital CDR Circuit With Unlimited Frequency Acquisition Capability in 65-nm CMOS.
IEEE J. Solid State Circuits, 2021
A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration.
IEEE J. Solid State Circuits, 2021
2019
A 15-GHz, 17.8-mW, 213-fs Injection-Locked PLL With Maximized Injection Strength Using Adjustment of Phase Domain Response.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
A 10-Gb/s, 0.03-mm<sup>2</sup>, 1.28-pJ/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology.
IEEE J. Solid State Circuits, 2019
A 4-to-20Gb/s 1.87pJ/b Referenceless Digital CDR With Unlimited Frequency Detection Capability in 65nm CMOS.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
A Synthesizable Digital AOT 4-Phase Buck Voltage Regulator for Digital Systems with 0.0054mm<sup>2</sup> Controller and 80ns Recovery Time.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
An Optimum Injection-Timing Tracking Loop for 5-GHz, 1.13-mW/GHz RO-Based Injection-Locked PLL With 152-fs Integrated Jitter.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
A 2.5-5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A 10-Gb/s, 0.03-mm<sup>2</sup>, 1.28-pJ/bit Half-Rate All-Digital Injection-Locked Clock and Data Recovery with Maximum Timing-Margin Tracking Loop.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
A 55.1 mW 1.62-to-8.1 Gb/s Video Interface Receiver Generating up to 680 MHz Stream Clock Over 20 dB Loss Channel.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
29.7 A 2.5GHz injection-locked ADPLL with 197fsrms integrated jitter and -65dBc reference spur using time-division dual calibration.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection.
Proceedings of the ESSCIRC Conference 2015, 2015