Han-Gon Ko

According to our database1, Han-Gon Ko authored at least 20 papers between 2015 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Online presence:

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Bibliography

2020
A 22-Gb/s 0.95-pJ/b Energy-Efficient Voltage-Mode Transmitter With Time-Based Feedforward Equalization in a 28-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2020

A 0.45 pJ/b, 6.4 Gb/s Forwarded-Clock Receiver With DLL-Based Self-Tracking Loop for Unmatched Memory Interfaces.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A 0.83-pJ/Bit 6.4-Gb/s HBM Base Die Receiver Using a 45° Strobe Phase for Energy-Efficient Skew Compensation.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A 0.1-pJ/b/dB 28-Gb/s Maximum-Eye Tracking, Weight-Adjusting MM CDR and Adaptive DFE with Single Shared Error Sampler.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

22.6 A 0.8-to-2.3GHz Quadrature Error Corrector with Correctable Error Range of 101.6ps Using Minimum Total Delay Tracking and Asynchronous Calibration On-Off Scheme for DRAM Interface.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

6.5 A 6.4-to-32Gb/s 0.96pJ/b Referenceless CDR Employing ML-Inspired Stochastic Phase-Frequency Detection Technique in 40nm CMOS.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

6.7 An 8Gb/s/µm FFE-Combined Crosstalk-Cancellation Scheme for HBM on Silicon Interposer with 3D-Staggered Channels.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019
A 15-GHz, 17.8-mW, 213-fs Injection-Locked PLL With Maximized Injection Strength Using Adjustment of Phase Domain Response.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

A 2.5-28 Gb/s Multi-Standard Transmitter With Two-Step Time-Multiplexing Driver.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

A 10-Gb/s, 0.03-mm<sup>2</sup>, 1.28-pJ/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology.
IEEE J. Solid State Circuits, 2019

Reference Spur Reduction Techniques for a Phase-Locked Loop.
IEEE Access, 2019

A 370-fJ/b, 0.0056 mm<sup>2</sup>/DQ, 4.8-Gb/s DQ Receiver for HBM3 with a Baud-Rate Self-Tracking Loop.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A Design of Data Path Based on CMOS Logic for a 72-Gb/s PAM-4 Transmitter in 28-nm CMOS.
Proceedings of the International Conference on Electronics, Information, and Communication, 2019

2018
25-Gb/s Clocked Pluggable Optics for High-Density Data Center Interconnections.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

An Optimum Injection-Timing Tracking Loop for 5-GHz, 1.13-mW/GHz RO-Based Injection-Locked PLL With 152-fs Integrated Jitter.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A 2.5-5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A 10-Gb/s, 0.03-mm<sup>2</sup>, 1.28-pJ/bit Half-Rate All-Digital Injection-Locked Clock and Data Recovery with Maximum Timing-Margin Tracking Loop.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017
29.7 A 2.5GHz injection-locked ADPLL with 197fsrms integrated jitter and -65dBc reference spur using time-division dual calibration.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016
A theoretical analysis of phase shift in pulse injection-locked oscillators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection.
Proceedings of the ESSCIRC Conference 2015, 2015


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