Kwanseo Park

Orcid: 0000-0002-4727-9868

According to our database1, Kwanseo Park authored at least 35 papers between 2000 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
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PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2023
A 48 Gb/s PAM-4 Receiver With Pre-Cursor Adjustable Baud-Rate Phase Detector in 40 nm CMOS.
IEEE J. Solid State Circuits, May, 2023

A 1.1-pJ/b 8-to-16-Gb/s Receiver With Stochastic CTLE Adaptation.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2023

A 12-Gbps, 0.24-pJ/b/dB PAM-4 Receiver With Dead-Zone Free SS-MMSE PD for CIS Link.
IEEE Access, 2023

2022
An Output Bandwidth Optimized 200-Gb/s PAM-4 100-Gb/s NRZ Transmitter With 5-Tap FFE in 28-nm CMOS.
IEEE J. Solid State Circuits, 2022

Design Techniques for a 6.4-32-Gb/s 0.96-pJ/b Continuous-Rate CDR With Stochastic Frequency-Phase Detector.
IEEE J. Solid State Circuits, 2022

Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR With Stochastic Phase Detector.
IEEE J. Solid State Circuits, 2022

A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in 28nm CMOS Technology.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021
An Adaptive Offset Cancellation Scheme and Shared-Summer Adaptive DFE for 0.068 pJ/b/dB 1.62-to-10 Gb/s Low-Power Receiver in 40 nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

A 4-20-Gb/s 1.87-pJ/b Continuous-Rate Digital CDR Circuit With Unlimited Frequency Acquisition Capability in 65-nm CMOS.
IEEE J. Solid State Circuits, 2021

A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration.
IEEE J. Solid State Circuits, 2021

A 10 Gb/s PAM-4 Transmitter With Feed-Forward Implementation of Tomlinson-Harashima Precoding in 28 nm CMOS.
IEEE Access, 2021

8 An Output-Bandwidth-Optimized 200Gb/s PAM-4 100Gb/s NRZ Transmitter with 5-Tap FFE in 28nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2020
A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s Video Interface Receiver With Jointly Adaptive CTLE and DFE Using Biased Data-Level Reference.
IEEE J. Solid State Circuits, 2020

6.5 A 6.4-to-32Gb/s 0.96pJ/b Referenceless CDR Employing ML-Inspired Stochastic Phase-Frequency Detection Technique in 40nm CMOS.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

6.7 An 8Gb/s/µm FFE-Combined Crosstalk-Cancellation Scheme for HBM on Silicon Interposer with 3D-Staggered Channels.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019
A Modulo-FIR Equalizer for Wireline Communications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A 15-GHz, 17.8-mW, 213-fs Injection-Locked PLL With Maximized Injection Strength Using Adjustment of Phase Domain Response.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

A 2.5-28 Gb/s Multi-Standard Transmitter With Two-Step Time-Multiplexing Driver.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

A 10-Gb/s, 0.03-mm<sup>2</sup>, 1.28-pJ/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology.
IEEE J. Solid State Circuits, 2019

A 4-to-20Gb/s 1.87pJ/b Referenceless Digital CDR With Unlimited Frequency Detection Capability in 65nm CMOS.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 0.1pJ/b/dB 1.62-to-10.8Gb/s Video Interface Receiver with Fully Adaptive Equalization Using Un-Even Data Level.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 64Gb/s 2.29pJ/b PAM-4 VCSEL Transmitter With 3-Tap Asymmetric FFE in 65nm CMOS.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

2018
A Supply-Scalable-Serializing Transmitter With Controllable Output Swing and Equalization for Next-Generation Standards.
IEEE Trans. Ind. Electron., 2018

A 2.44-pJ/b 1.62-10-Gb/s Receiver for Next Generation Video Interface Equalizing 23-dB Loss With Adaptive 2-Tap Data DFE and 1-Tap Edge DFE.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

25-Gb/s Clocked Pluggable Optics for High-Density Data Center Interconnections.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A 6.7-11.2 Gb/s, 2.25 pJ/bit, Single-Loop Referenceless CDR With Multi-Phase, Oversampling PFD in 65-nm CMOS.
IEEE J. Solid State Circuits, 2018

2017
A 55.1 mW 1.62-to-8.1 Gb/s Video Interface Receiver Generating up to 680 MHz Stream Clock Over 20 dB Loss Channel.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

A 27.1 mW, 7.5-to-11.1 Gb/s single-loop referenceless CDR with direct Up/dn control.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016
A 0.36 pJ/bit, 0.025 mm<sup>2</sup>, 12.5 Gb/s Forwarded-Clock Receiver With a Stuck-Free Delay-Locked Loop and a Half-Bit Delay Line in 65-nm CMOS Technology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS.
IEEE J. Solid State Circuits, 2016

A 6-to-32 Gb/s voltage-mode transmitter with scalable supply, voltage swing, and pre-emphasis in 65-nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop for 40-Gb/s serial link transmitter based on two-stage ring oscillator in 65-nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014
A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line.
Proceedings of the ESSCIRC 2014, 2014

2000
Stabilization of linear systems via low-order dynamic output feedback: a passification approach.
Proceedings of the American Control Conference, 2000


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