Kwangho Lee

According to our database1, Kwangho Lee authored at least 18 papers between 2005 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s Video Interface Receiver With Jointly Adaptive CTLE and DFE Using Biased Data-Level Reference.
IEEE J. Solid State Circuits, 2020

A 0.1-pJ/b/dB 28-Gb/s Maximum-Eye Tracking, Weight-Adjusting MM CDR and Adaptive DFE with Single Shared Error Sampler.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

2019
Memory streaming acceleration for embedded systems with CPU-accelerator cooperative data processing.
Microprocess. Microsystems, 2019

A 10-Gb/s, 0.03-mm<sup>2</sup>, 1.28-pJ/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology.
IEEE J. Solid State Circuits, 2019

A 4-to-20Gb/s 1.87pJ/b Referenceless Digital CDR With Unlimited Frequency Detection Capability in 65nm CMOS.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 0.1pJ/b/dB 1.62-to-10.8Gb/s Video Interface Receiver with Fully Adaptive Equalization Using Un-Even Data Level.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

2018
A 2.44-pJ/b 1.62-10-Gb/s Receiver for Next Generation Video Interface Equalizing 23-dB Loss With Adaptive 2-Tap Data DFE and 1-Tap Edge DFE.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

25-Gb/s Clocked Pluggable Optics for High-Density Data Center Interconnections.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

An Optimum Injection-Timing Tracking Loop for 5-GHz, 1.13-mW/GHz RO-Based Injection-Locked PLL With 152-fs Integrated Jitter.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

The effect of contents on sixth graders' understanding about the height of triangles.
Int. J. Knowl. Learn., 2018

A 10-Gb/s, 0.03-mm<sup>2</sup>, 1.28-pJ/bit Half-Rate All-Digital Injection-Locked Clock and Data Recovery with Maximum Timing-Margin Tracking Loop.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017
A 55.1 mW 1.62-to-8.1 Gb/s Video Interface Receiver Generating up to 680 MHz Stream Clock Over 20 dB Loss Channel.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

Using board games to improve mathematical creativity.
Int. J. Knowl. Learn., 2017

A DVFS-aware cache bypassing technique for multiple clock domain mobile SoCs.
IEICE Electron. Express, 2017

2016
Self-Adhesive and Capacitive Carbon Nanotube-Based Electrode to Record Electroencephalograph Signals From the Hairy Scalp.
IEEE Trans. Biomed. Eng., 2016

2014
Remarks on the Pocklington and Padró-Sáez Cube Root Algorithm in 𝔽<sub>q</sub>.
IACR Cryptol. ePrint Arch., 2014

2007
Durability improvement of polymer chamber of pulsatile extracorporeal life support system in terms of mechanical change.
Medical Biol. Eng. Comput., 2007

2005
Extraction of Representative Keywords Considering Co-occurrence in Positive Documents.
Proceedings of the Fuzzy Systems and Knowledge Discovery, Second International Conference, 2005


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