Kwangho Lee

Orcid: 0000-0001-6593-0354

According to our database1, Kwangho Lee authored at least 33 papers between 2005 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Identification of Location and Geometry of Invisible Internal Defects in Structures using Deep Learning and Surface Deformation Field.
Adv. Intell. Syst., December, 2023

A 48 Gb/s PAM-4 Receiver With Pre-Cursor Adjustable Baud-Rate Phase Detector in 40 nm CMOS.
IEEE J. Solid State Circuits, May, 2023

LPMM: Intuitive Pose Control for Neural Talking-Head Model via Landmark-Parameter Morphable Model.
CoRR, 2023

Chupa: Carving 3D Clothed Humans from Skinned Shape Priors using 2D Diffusion Probabilistic Models.
Proceedings of the IEEE/CVF International Conference on Computer Vision, 2023

2022
A 64-Gb/s PAM-4 Receiver With Transition-Weighted Phase Detector.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

A 2.5-32 Gb/s Gen 5-PCIe Receiver With Multi-Rate CDR Engine and Hybrid DFE.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR With Stochastic Phase Detector.
IEEE J. Solid State Circuits, 2022

Cross-Domain Style Mixing for Face Cartoonization.
CoRR, 2022

2021
An Adaptive Offset Cancellation Scheme and Shared-Summer Adaptive DFE for 0.068 pJ/b/dB 1.62-to-10 Gb/s Low-Power Receiver in 40 nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

A 4-20-Gb/s 1.87-pJ/b Continuous-Rate Digital CDR Circuit With Unlimited Frequency Acquisition Capability in 65-nm CMOS.
IEEE J. Solid State Circuits, 2021

Profiling Based I/O Optimization on the CE Devices.
Proceedings of the IEEE International Conference on Consumer Electronics, 2021

A 48 Gb/s PAM4 receiver with Baud-rate phase-detector for multi-level signal modulation in 40 nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

A 48Gb/s 2.4pJ/b PAM-4 Baud-Rate Digital CDR with Stochastic Phase Detection Technique in 40nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

A 64 Gb/s 2.09 pJ/b PAM-4 VCSEL Transmitter with Bandwidth Extension Techniques in 40 nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

2020
A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s Video Interface Receiver With Jointly Adaptive CTLE and DFE Using Biased Data-Level Reference.
IEEE J. Solid State Circuits, 2020

A 0.1-pJ/b/dB 28-Gb/s Maximum-Eye Tracking, Weight-Adjusting MM CDR and Adaptive DFE with Single Shared Error Sampler.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

A 8.4Gb/s Low Power Transmitter with 1.66 pJ/b using 40: 1 Serializer for DisplayPort Interface.
Proceedings of the International SoC Design Conference, 2020

2019
Memory streaming acceleration for embedded systems with CPU-accelerator cooperative data processing.
Microprocess. Microsystems, 2019

A 10-Gb/s, 0.03-mm<sup>2</sup>, 1.28-pJ/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology.
IEEE J. Solid State Circuits, 2019

A 4-to-20Gb/s 1.87pJ/b Referenceless Digital CDR With Unlimited Frequency Detection Capability in 65nm CMOS.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 0.1pJ/b/dB 1.62-to-10.8Gb/s Video Interface Receiver with Fully Adaptive Equalization Using Un-Even Data Level.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

2018
A 2.44-pJ/b 1.62-10-Gb/s Receiver for Next Generation Video Interface Equalizing 23-dB Loss With Adaptive 2-Tap Data DFE and 1-Tap Edge DFE.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

25-Gb/s Clocked Pluggable Optics for High-Density Data Center Interconnections.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

An Optimum Injection-Timing Tracking Loop for 5-GHz, 1.13-mW/GHz RO-Based Injection-Locked PLL With 152-fs Integrated Jitter.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

The effect of contents on sixth graders' understanding about the height of triangles.
Int. J. Knowl. Learn., 2018

A 10-Gb/s, 0.03-mm<sup>2</sup>, 1.28-pJ/bit Half-Rate All-Digital Injection-Locked Clock and Data Recovery with Maximum Timing-Margin Tracking Loop.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017
A 55.1 mW 1.62-to-8.1 Gb/s Video Interface Receiver Generating up to 680 MHz Stream Clock Over 20 dB Loss Channel.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

Using board games to improve mathematical creativity.
Int. J. Knowl. Learn., 2017

A DVFS-aware cache bypassing technique for multiple clock domain mobile SoCs.
IEICE Electron. Express, 2017

2016
Self-Adhesive and Capacitive Carbon Nanotube-Based Electrode to Record Electroencephalograph Signals From the Hairy Scalp.
IEEE Trans. Biomed. Eng., 2016

2014
Remarks on the Pocklington and Padró-Sáez Cube Root Algorithm in 𝔽<sub>q</sub>.
IACR Cryptol. ePrint Arch., 2014

2007
Durability improvement of polymer chamber of pulsatile extracorporeal life support system in terms of mechanical change.
Medical Biol. Eng. Comput., 2007

2005
Extraction of Representative Keywords Considering Co-occurrence in Positive Documents.
Proceedings of the Fuzzy Systems and Knowledge Discovery, Second International Conference, 2005


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