Sonia López

According to our database1, Sonia López authored at least 33 papers between 2003 and 2021.

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Bibliography

2021
A Modified Version of K-Means Algorithm.
Proceedings of the Advances on P2P, Parallel, Grid, Cloud and Internet Computing, 2021

2020
Artificial Moral Agents: A Survey of the Current Status.
Sci. Eng. Ethics, 2020

The plausibility of using unmanned aerial vehicles as a serious game for dealing with attention deficit-hyperactivity disorder.
Cogn. Syst. Res., 2020

Toward ethical cognitive architectures for the development of artificial moral agents.
Cogn. Syst. Res., 2020

2019
Brain-Computer Interfaces for Controlling Unmanned Aerial Vehicles: Computational Tools for Cognitive Training.
Proceedings of the Biologically Inspired Cognitive Architectures 2019, 2019

2017
Integrating a cognitive computational model of planning and decision-making considering affective information.
Cogn. Syst. Res., 2017

Alternative Processor Within Threshold: Flexible Scheduling on Heterogeneous Systems.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

Power Analysis of HLS-Designed Customized Instruction Set Architectures.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

2016
Autonomous Agents and Ethical Decision-Making.
Cogn. Comput., 2016

2015
Designing customized ISA processors using high level synthesis.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

A Parallelizing Matlab Compiler Framework and Run Time for Heterogeneous Systems.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

A unified hardware/software MPSoC system construction and run-time framework.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

A cognitive model of motor planning for virtual creatures.
Proceedings of the 14th IEEE International Conference on Cognitive Informatics & Cognitive Computing, 2015

2014
Performance modeling of pipelined linear algebra architectures on FPGAs.
Comput. Electr. Eng., 2014

Mission control: A performance metric and analysis of control logic for pipelined architectures on FPGAs.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

Enabling FPGA support in Matlab based heterogeneous systems.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

2013
Cognitive Process of Moral Decision-Making for Autonomous Agents.
Int. J. Softw. Sci. Comput. Intell., 2013

Distributed execution of transmural electrophysiological imaging with CPU, GPU, and FPGA.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

Linear algebra computations in heterogeneous systems.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013

Performance Modeling of Pipelined Linear Algebra Architectures on FPGAs.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013

A biologically inspired computational model of Moral Decision Making for autonomous agents.
Proceedings of the IEEE 12th International Conference on Cognitive Informatics and Cognitive Computing, 2013

2011
A phase adaptive cache hierarchy for SMT processors.
Microprocess. Microsystems, 2011

2010
Adaptive Cache Memories for SMT Processors.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009
Improving SMT performance: an application of genetic algorithms to configure resizable caches.
Proceedings of the Genetic and Evolutionary Computation Conference, 2009

2007
Reducing power of functional units in high-performance processors by checking instruction codes and resizing adders.
IET Comput. Digit. Tech., 2007

Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches.
Proceedings of the High Performance Embedded Architectures and Compilers, 2007

Rate-Driven Control of Resizable Caches for Highly Threaded SMT Processors.
Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007

2006
A Technique to Reduce Static and Dynamic Power of Functional Units in High-Performance Processors.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Sim-async: An Architectural Simulator for Asynchronous Processor Modeling Using Distribution Functions.
Proceedings of the Euro-Par 2006, Parallel Processing, 12th International Euro-Par Conference, Dresden, Germany, August 28, 2006

Comparing the Performance of a 64-bit Fully-Asynchronous Superscalar Processor versus its Synchronous Counterpart.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

2004
Empirical Characterization of the Latency of Long Asynchronous Pipelines with Data-Dependent Module Delays.
Proceedings of the 12th Euromicro Workshop on Parallel, 2004

Enhancing GALS Processor Performance Using Data Classification Based on Data Latency.
Proceedings of the Integrated Circuit and System Design, 2004

2003
Power-Consumption RRRRreduction in Asynchronous Circuits Using Delay Path Unequalization.
Proceedings of the Integrated Circuit and System Design, 2003


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