Román Hermida

According to our database1, Román Hermida authored at least 91 papers between 1992 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
Evaluation of blood pressure estimation models based on pulse arrival time.
Comput. Electr. Eng., 2020

2019
A Combined Arithmetic-High-Level Synthesis Solution to Deploy Partial Carry-Save Radix-8 Booth Multipliers in Datapaths.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Efficient Mitchell's Approximate Log Multipliers for Convolutional Neural Networks.
IEEE Trans. Computers, 2019

Modular framework to model critical events in stroke patients.
Proceedings of the 2019 Summer Simulation Conference, 2019

2018
A Modular Low-Complexity ECG Delineation Algorithm for Real-Time Embedded Systems.
IEEE J. Biomed. Health Informatics, 2018

Complexity reduction in the HEVC/H265 standard based on smooth region classification.
Digit. Signal Process., 2018

Low-power implementation of Mitchell's approximate logarithmic multiplication for convolutional neural networks.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Reconsidering the performance of DEVS modeling and simulation environments using the DEVStone benchmark.
Simul., 2017

A slack-based approach to efficiently deploy radix 8 booth multipliers.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
A Distributed Clustered Architecture to Tackle Delay Variations in Datapath Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

A Partial Carry-Save On-the-Fly Correction Multispeculative Multiplier.
IEEE Trans. Computers, 2016

Runtime data center temperature prediction using Grammatical Evolution techniques.
Appl. Soft Comput., 2016

2014
Ultra-low-power adder stage design for exascale floating point units.
ACM Trans. Embed. Comput. Syst., 2014

Improving circuit performance with multispeculative additive trees in high-level synthesis.
Microelectron. J., 2014

Generic Markov model of the contention access period of IEEE 802.15.4 MAC layer.
Digit. Signal Process., 2014

2013
Low complexity bit-parallel polynomial basis multipliers over binary fields for special irreducible pentanomials.
Integr., 2013

A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths.
Integr., 2013

Exploring the energy efficiency of Multispeculative Adders.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Multispeculative additive trees in high-level synthesis.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Multispeculative Addition Applied to Datapath Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

2011
A Distributed Controller for Managing Speculative Functional Units in High Level Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Power optimization in heterogenous datapaths.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
Using Speculative Functional Units in high level synthesis.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Frequent-Pattern-Guided Multilevel Decomposition of Behavioral Specifications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

A framework for low energy data management in reconfigurable multi-context architectures.
J. Syst. Archit., 2009

2008
Scheduling methodology for conditional execution of kernels onto multicontext reconfigurable architectures.
IET Comput. Digit. Tech., 2008

Applying speculation techniques to implement functional units.
Proceedings of the 26th International Conference on Computer Design, 2008

Restricted Chaining and Fragmentation Techniques in Power Aware High Level Synthesis.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2007
HW-SW emulation framework for temperature-aware design in MPSoCs.
ACM Trans. Design Autom. Electr. Syst., 2007

Area optimization of multi-cycle operators in high-level synthesis.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Low Complexity Bit-Parallel Multipliers Based on a Class of Irreducible Pentanomials.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Bitwise scheduling to balance the computational cost of behavioral specifications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Configuration Scheduling for Conditional Branch Execution Onto Multi-Context Reconfigurable Architectures.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Pre-synthesis optimization of multiplications to improve circuit performance.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Versatile FPGA-Based Functional Validation Framework for Networks-on-Chip Interconnections Designs.
Proceedings of the Parallel Computing: Current & Future Issues of High-End Computing, 2005

A novel approach for network on chip emulation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Low Power Data Prefetch for 3D Image Applications on Coarse-Grain Reconfigurable Architectures.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Performance-driven read-after-write dependencies softening in high-level synthesis.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis.
Proceedings of the 2005 Design, 2005

A Complete Network-On-Chip Emulation Framework.
Proceedings of the 2005 Design, 2005

Arrival time aware scheduling to minimize clock cycle length.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Annealing placement by thermodynamic combinatorial optimization.
ACM Trans. Design Autom. Electr. Syst., 2004

Empirical Characterization of the Latency of Long Asynchronous Pipelines with Data-Dependent Module Delays.
Proceedings of the 12th Euromicro Workshop on Parallel, 2004

Behavioural Scheduling to Balance the Bit-Level Computational Effort.
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

Behavioural Bitwise Scheduling Based on Computational Effort Balancing.
Proceedings of the 2004 Design, 2004

Efficient mapping of hierarchical trees on coarse-grain reconfigurable architectures.
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

2003
Allocation of multiple precision behaviors for maximal bit level reuse of hardware resources.
J. Syst. Archit., 2003

Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis.
Proceedings of the Integrated Circuit and System Design, 2003

Power-Consumption RRRRreduction in Asynchronous Circuits Using Delay Path Unequalization.
Proceedings of the Integrated Circuit and System Design, 2003

Multi-FPGA Systems Synthesis by Means of Evolutionary Computation.
Proceedings of the Genetic and Evolutionary Computation, 2003

Low Energy Data Management for Different On-Chip Memory Levels in Multi-Context Reconfigurable Architectures.
Proceedings of the 2003 Design, 2003

High-Level Allocation to Minimize Internal Hardware Wastage.
Proceedings of the 2003 Design, 2003

2002
A global approach to improve conditional hardware reuse in high-level synthesis.
J. Syst. Archit., 2002

A study about the efficiency of formal high-level synthesis applied to verification.
Integr., 2002

Optimization of Asynchronous Delay-Insensitive Pipeline Latency Using Stage Reorganization and Optimal Stage Parameter Estimation.
Fundam. Informaticae, 2002

A New Methodology to Design Low-Power Asynchronous Circuits.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Bit-level scheduling of heterogeneous behavioural specifications.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Transformation of Equational Specification by Means of Genetic Programming.
Proceedings of the Genetic Programming, 5th European Conference, 2002

Source Code Transformation to Improve Conditional Hardware Reuse.
Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002

Bit-Level Allocation of Multiple-Precision Specifications.
Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002

Efficient Verification of Scheduling, Allocation and Binding in High-Level Synthesis.
Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002

Optimization of Equational Specifications Using Genetic Techniques.
Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002

A Hybrid Evolutionary Algorithm for Multi-FPGA Systems Design.
Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002

FPGA Placement by Thermodynamic Combinatorial Optimization.
Proceedings of the 2002 Design, 2002

A Complete Data Scheduler for Multi-Context Reconfigurable Architectures.
Proceedings of the 2002 Design, 2002

Maximizing Conditonal Reuse by Pre-Synthesis Transformations.
Proceedings of the 2002 Design, 2002

Multiple-Precision Circuits Allocation Independent of Data-Objects Length.
Proceedings of the 2002 Design, 2002

High-level synthesis of multiple-precision circuitsindependent of data-objects length.
Proceedings of the 39th Design Automation Conference, 2002

2001
A framework for reconfigurable computing: task scheduling and context management.
IEEE Trans. Very Large Scale Integr. Syst., 2001

A formal approach to context scheduling for multicontext reconfigurable architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2001

Kernel scheduling techniques for efficient solution space exploration in reconfigurable computing.
J. Syst. Archit., 2001

A data scheduler for multi-context reconfigurable architectures.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

A pseudo delay-insensitive timing model to synthesizing low-power asynchronous circuits.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000
Adaptive FPGA Placement by Natural Optimization.
Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000), 2000

Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures.
Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

Partitioning and Placement for Multi-FPGA Systems Using Genetic Algorithms.
Proceedings of the 26th EUROMICRO 2000 Conference, 2000

1999
A Framework for Scheduling and Context Allocation in Reconfigurable Computing.
Proceedings of the 12th International Symposium on System Synthesis, 1999

Placement Optimization Based on Global Routing Updating for System Partitioning onto Multi-FPGA Mesh Topologies.
Proceedings of the Field-Programmable Logic and Applications, 9th International Workshop, 1999

A Unified Algorithm for Mutual Exclusiveness Identification.
Proceedings of the 25th EUROMICRO '99 Conference, 1999

The Heterogeneous Structure Problem in Hardware/Software Codesign: A Macroscopic Approach.
Proceedings of the 1999 Design, 1999

Kernel Scheduling in Reconfigurable Computing.
Proceedings of the 1999 Design, 1999

1998
RSR: A New Rectilinear Steiner Minimum Tree Approximation for FPGA Placement and Global Routing.
Proceedings of the 24th EUROMICRO '98 Conference, 1998

Correct High-Level Synthesis: a Formal Perspective.
Proceedings of the 1998 Design, 1998

1997
A unified approach for scheduling and allocation.
Integr., 1997

Formal Techniques for Hardware Allocation.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

1996
Register estimation in unscheduled dataflow graphs.
ACM Trans. Design Autom. Electr. Syst., 1996

Algebraic Support for Transformational Hardware Allocation.
Proceedings of the 1996 European Design and Test Conference, 1996

1994
Clock cycle estimation based on dead time and control unit area minimization.
Microprocess. Microprogramming, 1994

1993
Global hardware synthesis guided by realistic probability computation.
Microprocess. Microprogramming, 1993

An approach to module binding by fuzzy partitioning.
Proceedings of the European Design Automation Conference 1993, 1993

1992
Heuristics for branch-and-bound global allocation.
Proceedings of the conference on European design automation, 1992


  Loading...