Sotirios G. Ziavras

According to our database1, Sotirios G. Ziavras
  • authored at least 104 papers between 1986 and 2017.
  • has a "Dijkstra number"2 of five.

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Bibliography

2017
Instruction Fusion for Multiscalar and Many-Core Processors.
International Journal of Parallel Programming, 2017

2016
Vector Coprocessor Virtualization for Simultaneous Multithreading.
ACM Trans. Embedded Comput. Syst., 2016

Power-Performance Optimization of a Virtualized SMT Vector Processor via Thread Fusion and Lane Configuration.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

2015
Performance-Energy Optimizations for Shared Vector Accelerators in Multicores.
IEEE Trans. Computers, 2015

A Method to Measure Packet Processing Time of Hosts Using High-Speed Transmission Lines.
IEEE Systems Journal, 2015

Modular vector processor architecture targeting at data-level parallelism.
Microprocessors and Microsystems - Embedded Hardware Design, 2015

A multiprocessor-on-a-programmable-chip reconfigurable system for matrix operations with power-grid case studies.
IJCSE, 2015

2014
ASIC Design of Shared Vector Accelerators for Multicore Processors.
Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing, 2014

2013
Multicore-based vector coprocessor sharing for performance and energy gains.
ACM Trans. Embedded Comput. Syst., 2013

Efficient on-chip vector processing for multicore processors.
Proceedings of the 2013 International Symposium on System on Chip, 2013

Packet classification using rule caching.
Proceedings of the 4th International Conference on Information, 2013

FPGA and ASIC square root designs for high performance and power efficiency.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013

2012
Novel Pipelined Architecture for Efficient Evaluation of the Square Root Using a Modified Non-Restoring Algorithm.
Signal Processing Systems, 2012

Replicating Tag Entries for Reliability Enhancement in Cache Tag Arrays.
IEEE Trans. VLSI Syst., 2012

Versatile design of shared vector coprocessors for multicores.
Microprocessors and Microsystems - Embedded Hardware Design, 2012

Exploring branch target buffer access filtering for low-energy and high-performance microarchitectures.
IET Computers & Digital Techniques, 2012

Message from General Chairs.
Proceedings of the IEEE 24th International Conference on Tools with Artificial Intelligence, 2012

2011
On-chip Vector Coprocessor Sharing for Multicores.
Proceedings of the 19th International Euromicro Conference on Parallel, 2011

2010
Online anonymity protection in computer-mediated communication.
IEEE Trans. Information Forensics and Security, 2010

Scheduling for input-queued packet switches by a re-configurable parallel match evaluator.
IEEE Communications Letters, 2010

Efficient hardware support for pattern matching in network intrusion detection.
Computers & Security, 2010

Novel FPGA-Based Signature Matching for Deep Packet Inspection.
Proceedings of the Information Security Theory and Practices. Security and Privacy of Pervasive Systems and Smart Devices, 2010

FPGA-based Normalization for Modified Gram-Schmidt Orthogonalization.
Proceedings of the VISAPP 2010 - Proceedings of the Fifth International Conference on Computer Vision Theory and Applications, Angers, France, May 17-21, 2010, 2010

TRB: Tag Replication Buffer for Enhancing the Reliability of the Cache Tag Array.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Hardware-Based Speed Up of Face Recognition Towards Real-Time Performance.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009
On the Exploitation of Narrow-Width Values for Improving Register File Reliability.
IEEE Trans. VLSI Syst., 2009

On the Characterization and Optimization of On-Chip Cache Reliability against Soft Errors.
IEEE Trans. Computers, 2009

Customized kernel execution on reconfigurable hardware for embedded applications.
Microprocessors and Microsystems - Embedded Hardware Design, 2009

Designing for different levels of social inference risk.
Proceedings of the 5th Symposium on Usable Privacy and Security, 2009

Preventing Unwanted Social Inferences with Classification Tree Analysis.
Proceedings of the ICTAI 2009, 2009

Re-Configurable Parallel Match Evaluators Applied to Scheduling Schemes for Input-Queued Packet Switches.
Proceedings of the 18th International Conference on Computer Communications and Networks, 2009

Identity Inference as a Privacy Risk in Computer-Mediated Communication.
Proceedings of the 42st Hawaii International International Conference on Systems Science (HICSS-42 2009), 2009

Exploiting narrow-width values for thermal-aware register file designs.
Proceedings of the Design, Automation and Test in Europe, 2009

Social Inference Risk Modeling in Mobile and Social Applications.
Proceedings of the 12th IEEE International Conference on Computational Science and Engineering, 2009

2008
Robust scalability analysis and SPM case studies.
The Journal of Supercomputing, 2008

Self-Adaptive Data Caches for Soft-Error Reliability.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Asymmetrically banked value-aware register files for low-energy and high-performance.
Microprocessors and Microsystems - Embedded Hardware Design, 2008

Generalized Anomaly Detection Model for Windows-based Malicious Program Behavior .
I. J. Network Security, 2008

BTB Access Filtering: A Low Energy and High Performance Design.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

2007
Partially Reconfigurable Vector Processor for Embedded Applications.
JCP, 2007

Coprocessor design to support MPI primitives in configurable multiprocessors.
Integration, 2007

Reconfiguration support for vector operations.
IJHPSA, 2007

FPGA-based Vector Processing for Matrix Operations.
Proceedings of the Fourth International Conference on Information Technology: New Generations (ITNG 2007), 2007

Runtime Partial Reconfiguration for Embedded Vector Processors.
Proceedings of the Fourth International Conference on Information Technology: New Generations (ITNG 2007), 2007

Vector Processing Support for FPGA-Oriented High Performance Applications.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Asymmetrically Banked Value-Aware Register Files.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Performance-Energy Tradeoffs for Matrix Multiplication on FPGA-Based Mixed-Mode Chip Multiprocessors.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

A Study of Data Exchange Protocols for the Grid Computing Environment.
Proceedings of the Third International Conference on Networking and Services (ICNS 2007), 2007

Measuring Network Parameters with Hardware Support.
Proceedings of the Third International Conference on Networking and Services (ICNS 2007), 2007

Resource management for dynamically-challenged reconfigurable systems.
Proceedings of 12th IEEE International Conference on Emerging Technologies and Factory Automation, 2007

Energy-Aware System Synthesis for Reconfigurable Chip Multiprocessors.
Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007

2006
A Coarse-Grain Hierarchical Technique for 2-Dimensional FFT on Configurable Parallel Computers.
IEICE Transactions, 2006

On the Characterization of Data Cache Vulnerability in High-Performance Embedded Microprocessors.
Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, 2006

System-Level Energy Modeling for Heterogeneous Reconfigurable Chip Multiprocessors.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

In-Register Duplication: Exploiting Narrow-Width Value for Improving Register File Reliability.
Proceedings of the 2006 International Conference on Dependable Systems and Networks (DSN 2006), 2006

2005
Modeling distributed data representation and its effect on parallel data accesses.
J. Parallel Distrib. Comput., 2005

FPGA-based vector processor for algebraic equation solvers.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

A hierarchically-controlled SIMD machine for 2D DCT on FPGAs.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

H-SIMD Machine: Configurable Parallel Computing for Matrix Multiplication.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Optimizing the Thermal Behavior of Subarrayed Data Caches.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Load-balanced CICB packet switch with support for long round-trip times.
Proceedings of the Global Telecommunications Conference, 2005. GLOBECOM '05, St. Louis, Missouri, USA, 28 November, 2005

A Framework for Dynamic Resource Assignment and Scheduling on Reconfigurable Mixed-Mode On-Chip Multiprocessors.
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

FPGA-Based Vector Processing for Solving Sparse Sets of Equations.
Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005

An FPGA-Based Parallel Accelerator for Matrix Multiplications in the Newton-Raphson Method.
Proceedings of the Embedded and Ubiquitous Computing, 2005

Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures.
Proceedings of the Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, 2005

2004
A Super-Programming Approach for Mining Association Rules in Parallel on PC Clusters.
IEEE Trans. Parallel Distrib. Syst., 2004

FPGA implementation of a Cholesky algorithm for a shared-memory multiprocessor architecture.
Parallel Algorithms Appl., 2004

A Super-Programming Technique for Large Sparse Matrix Multiplication on PC Clusters.
IEICE Transactions, 2004

Parallel LU factorization of sparse matrices on FPGA-based configurable computing engines.
Concurrency and Computation: Practice and Experience, 2004

A Configurable Multiprocessor and Dynamic Load Balancing for Parallel LU Factorization.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

2003
Processor design based on dataflow concurrency.
Microprocessors and Microsystems, 2003

Viable Architectures for High-Performance Computing.
Comput. J., 2003

Parallel Direct Solution of Linear Equations on FPGA-Based Machines.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

Load Balancing on PC Clusters with the Super-Programming Model.
Proceedings of the 32nd International Conference on Parallel Processing Workshops (ICPP 2003 Workshops), 2003

Performance optimization of an FPGA-based configurable multiprocessor for matrix operations.
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003

Iterative Methods for Solving Linear Systems of Equations on FPGA-Based Machines.
Proceedings of the ISCA 18th International Conference Computers and Their Applications, 2003

2002
Dataflow computation with intelligent memories emulated on field-programmable gate arrays (FPGAs).
Microprocessors and Microsystems, 2002

2000
A new-generation parallel computer and its performance evaluation.
Future Generation Comp. Syst., 2000

Versatile Processor Design for Efficiency and High Performance.
Proceedings of the 5th International Symposium on Parallel Architectures, 2000

1999
Evaluating the communications capabilities of the generalized hypercube interconnection network.
Concurrency - Practice and Experience, 1999

Powerful and Feasible Processor Interconnections With an Evaluation of Their Communications Capabilities.
Proceedings of the 1999 International Symposium on Parallel Architectures, 1999

Network Embedding Techniques for a New Class of Feasible Parallel Architectures.
Proceedings of the 17th IASTED International Conference on Applied Informatics, 1999

1998
Robust interprocessor connections for very-high performance.
Proceedings of the Robust Communication Networks: Interconnection and Survivability, 1998

1997
Parallel generation of adaptive multiresolution structures for image processing.
Concurrency - Practice and Experience, 1997

1996
Data Broadcasting and Reduction, Prefix Computation, and Sorting on Reduces Hypercube Parallel Computer.
Parallel Computing, 1996

Parallel DSP algorithms on TurboNet: an experimental system with hybrid message-passing/shared-memory architecture.
Concurrency - Practice and Experience, 1996

Performance Analysis for an Important Class of Parallel-Processing Networks.
Proceedings of the 1996 International Symposium on Parallel Architectures, 1996

1995
Scalable Multifolded Hypercubes for versatile Parallel Computers.
Parallel Processing Letters, 1995

Facilitating High-Performance Image Analysis on Reduced Hypercube (RH) Parallel Computers.
IJPRAI, 1995

1994
RH: A Versatile Family of Reduced Hypercube Interconnection Networks.
IEEE Trans. Parallel Distrib. Syst., 1994

Adaptive Multiresolution Structures for Image Processing on Parallel Computers.
J. Parallel Distrib. Comput., 1994

High-performance emulation of hierarchical structures on hypercube supercomputers.
Concurrency - Practice and Experience, 1994

A class of scalable architectures for high-performance, cost-effective parallel computing.
Proceedings of the Sixth IEEE Symposium on Parallel and Distributed Processing, 1994

Generalized reduced hypercube interconnection networks for massivelyparallel computers.
Proceedings of the Workshop on Interconnection Networks and Mapping and Scheduling Parallel Computations, 1994

1993
Efficient Mapping Algorithms for a Class of Hierarchical Systems.
IEEE Trans. Parallel Distrib. Syst., 1993

Connected component labelling on the BLITZEN massively parallel processor.
Image Vision Comput., 1993

Pyramid mappings onto hypercubes for computer vision: Connection machine comparative study.
Concurrency - Practice and Experience, 1993

1992
On the Problem of Expanding Hypercube-Based Systems.
J. Parallel Distrib. Comput., 1992

Processor Allocation for a Class of Hypercube-Like Supercomputers.
Proceedings of the Proceedings Supercomputing '92, 1992

Connection Machine Results for Pyramid Embedding Algorithms.
Proceedings of the Parallel Processing: CONPAR 92, 1992

1990
Techniques for Mapping Deterministic Algorithms onto Multi-Level Systems.
Proceedings of the 1990 International Conference on Parallel Processing, 1990

1989
On the mapping problem for multi-level systems.
Proceedings of the Proceedings Supercomputing '89, Reno, NV, USA, November 12-17, 1989, 1989

1988
Improved algorithms for translation of pictures represented by leaf codes.
Image Vision Comput., 1988

1986
Architectural Adaptations for Hierarchical Image Processing/Transmission.
ICC, 1986


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