Greg M. Link

According to our database1, Greg M. Link authored at least 19 papers between 2003 and 2009.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2009
Design of Thermally Robust Clock Trees Using Dynamically Adaptive Clock Buffers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

2007
Mitigating Thermal Effects on Clock Skew with Dynamically Adaptive Drivers.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Load Miss Prediction - Exploiting Power Performance Trade-offs.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Thermally robust clocking schemes for 3D integrated circuits.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Poster reception - Energy/performance modeling for collective communication in 3-D torus cluster networks.
Proceedings of the ACM/IEEE SC2006 Conference on High Performance Networking and Computing, 2006

Thermal Trends in Emerging Technologies.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Interconnect and Thermal-aware Floorplanning for 3D Microprocessors.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

2005
A Holistic Approach to Designing Energy-Efficient Cluster Interconnects.
IEEE Trans. Computers, 2005

Networks on Chip (NoC): Interconnects of Next Generation Systems on Chip.
Adv. Comput., 2005

Implementing LDPC Decoding on Network-on-Chip.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Temperature-Aware Voltage Islands Architecting in System-on-Chip Design.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Hotspot Prevention Through Runtime Reconfiguration in Network-On-Chip.
Proceedings of the 2005 Design, 2005

FD-HGAC: a hybrid heuristic/genetic algorithm hardware/software co-synthesis framework with fault detection.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures.
Proceedings of the Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, 2005

2004
Embedded Hardware Face Detection.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

A generic reconfigurable neural network architecture as a network on chip.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

Evaluating Alternative Implementations for LDPC Decoder Check Node Function.
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

Fault Tolerant Algorithms for Network-On-Chip Interconnect.
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

2003
Energy optimization techniques in cluster interconnects.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003


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