Noah Hae-Woong Yang

According to our database1, Noah Hae-Woong Yang authored at least 8 papers between 2013 and 2019.

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Bibliography

2019
A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR- and IIR-Tap Adaptation in 65-nm CMOS.
J. Solid-State Circuits, 2019

2018
A 56 Gb/s PAM4 receiver with low-overhead threshold and edge-based DFE FIR and IIR-tap adaptation in 65nm CMOS.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2017
A Reconfigurable 16/32 Gb/s Dual-Mode NRZ/PAM4 SerDes in 65-nm CMOS.
J. Solid-State Circuits, 2017

A low-power dual-mode 20-Gb/s NRZ and 28-Gb/s PAM-4 voltage-mode transmitter.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2015
A 32 Gb/s 0.55 mW/Gbps PAM4 1-FIR 2-IIR tap DFE receiver in 65-nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2015

2014
An 8-16 Gb/s, 0.65-1.05 pJ/b, Voltage-Mode Transmitter With Analog Impedance Modulation Equalization and Sub-3 ns Power-State Transitioning.
J. Solid-State Circuits, 2014

2013
A 6-b 1.6-GS/s ADC With Redundant Cycle One-Tap Embedded DFE in 90-nm CMOS.
J. Solid-State Circuits, 2013

A 0.47-0.66 pJ/bit, 4.8-8 Gb/s I/O Transceiver in 65 nm CMOS.
J. Solid-State Circuits, 2013


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