Srihari Cadambi

According to our database1, Srihari Cadambi authored at least 34 papers between 1998 and 2014.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2014
A Coprocessor Sharing-Aware Scheduler for Xeon Phi-Based Compute Clusters.
Proceedings of the 2014 IEEE 28th International Parallel and Distributed Processing Symposium, 2014

2013
COSMIC: middleware for high performance and reliable multiprocessing on xeon phi coprocessors.
Proceedings of the 22nd International Symposium on High-Performance Parallel and Distributed Computing, 2013

2012
A Massively Parallel, Energy Efficient Programmable Accelerator for Learning and Classification.
ACM Trans. Archit. Code Optim., 2012

Kernel Weaver: Automatically Fusing Database Primitives for Efficient GPU Computation.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

Optimizing Data Warehousing Applications for GPUs Using Kernel Fusion/Fission.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

Interference-driven resource management for GPU-based heterogeneous clusters.
Proceedings of the 21st International Symposium on High-Performance Parallel and Distributed Computing, 2012

2011
An Energy-Efficient Heterogeneous System for Embedded Learning and Classification.
IEEE Embed. Syst. Lett., 2011

A parallel accelerator for semantic search.
Proceedings of the IEEE 9th Symposium on Application Specific Processors, 2011

Power management for heterogeneous clusters: An experimental study.
Proceedings of the 2011 International Green Computing Conference and Workshops, 2011

Symphony: A Scheduler for Client-Server Applications on Coprocessor-Based Heterogeneous Clusters.
Proceedings of the 2011 IEEE International Conference on Cluster Computing (CLUSTER), 2011

2010
Data-aware scheduling of legacy kernels on heterogeneous platforms with distributed memory.
Proceedings of the SPAA 2010: Proceedings of the 22nd Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2010

A dynamically configurable coprocessor for convolutional neural networks.
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

Best-effort semantic document search on GPUs.
Proceedings of 3rd Workshop on General Purpose Processing on Graphics Processing Units, 2010

A programmable parallel accelerator for learning and classification.
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

2009
A hybrid nano-CMOS architecture for defect and fault tolerance.
ACM J. Emerg. Technol. Comput. Syst., 2009

Using hardware transactional memory for data race detection.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

A Massively Parallel FPGA-Based Coprocessor for Support Vector Machines.
Proceedings of the FCCM 2009, 2009

A Massively Parallel Coprocessor for Convolutional Neural Networks.
Proceedings of the 20th IEEE International Conference on Application-Specific Systems, 2009

2008
Bitwidth Reduction via Symbolic Interval Analysis for Software Model Checking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Fault-Tolerant Computing Using a Hybrid Nano-CMOS Architecture.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

RaceTM: detecting data races using transactional memory.
Proceedings of the SPAA 2008: Proceedings of the 20th Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2008

A Massively Parallel Digital Learning Processor.
Proceedings of the Advances in Neural Information Processing Systems 21, 2008

2007
Memory-Efficient Regular Expression Search Using State Merging.
Proceedings of the INFOCOM 2007. 26th IEEE International Conference on Computer Communications, 2007

2006
Chisel: A Storage-efficient, Collision-free Hash-based Network Processing Architecture.
Proceedings of the 33rd International Symposium on Computer Architecture (ISCA 2006), 2006

Power analysis of mobile 3D graphics.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Signature-based workload estimation for mobile 3D graphics.
Proceedings of the 43rd Design Automation Conference, 2006

2002
A fast, inexpensive and scalable hardware acceleration technique for functional simulation.
Proceedings of the 39th Design Automation Conference, 2002

2001
Static Profile-Driven Compilation for FPGAs.
Proceedings of the Field-Programmable Logic and Applications, 2001

2000
Pipeline Reconfigurable FPGAs.
J. VLSI Signal Process., 2000

PipeRench: A Reconfigurable Architecture and Compiler.
Computer, 2000

Efficient Place and Route for Pipeline Reconfigurable Architectures.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

1999
PipeRench: A Coprocessor for Streaming multimedia Acceleration.
Proceedings of the 26th Annual International Symposium on Computer Architecture, 1999

CPR: A Configuration Profiling Tool.
Proceedings of the 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 1999

1998
Managing Pipeline-Reconfigurable FPGAs.
Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998


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