Herman Schmit

According to our database1, Herman Schmit authored at least 48 papers between 1993 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2019
Spatial Timing Analysis With Exact Propagation of Delay and Application to FPGA Performance.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

2017
3.3 A 14nm 1GHz FPGA with 2.5D transceiver integration.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016
Dissecting Xeon + FPGA: Why the integration of CPUs and FPGAs makes a power difference for the datacenter: Invited Paper.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Stratix™ 10 High Performance Routable Clock Networks.
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

2008
Placement challenges for structured ASICs.
Proceedings of the 2008 International Symposium on Physical Design, 2008

2005
Layout techniques for FPGA switch blocks.
IEEE Trans. Very Large Scale Integr. Syst., 2005

2004
A low power approach to system level pipelined interconnect design.
Proceedings of the Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), 2004

Evaluating Alternative Implementations for LDPC Decoder Check Node Function.
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

Creating a power-aware structured ASIC.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

A power aware system level interconnect design methodology for latency-insensitive systems.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

An Interconnect Channel Design Methodology for High Performance Integrated Circuits.
Proceedings of the 2004 Design, 2004

Enabling energy efficiency in via-patterned gate array devices.
Proceedings of the 41th Design Automation Conference, 2004

2003
The Sandbox Design Experience Course.
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

CAD Tool Support For A Multi-University Soc Certificate Program: The Digital Sandbox.
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

An architectural exploration of via patterned gate arrays.
Proceedings of the 2003 International Symposium on Physical Design, 2003

Floorplanning of pipelined array modules using sequence pairs.
Proceedings of the 2003 International Symposium on Physical Design, 2003

Heterogeneous Logic Block Architectures for Via-Patterned Programmable Fabrics.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Efficient Application Representation for HASTE: Hybrid Architectures with a Single, Transformable Executable.
Proceedings of the 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 2003

Asynchronous PipeRench: Architecture and Performance Estimations.
Proceedings of the 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 2003

Heterogeneous Programmable Logic Block Architectures.
Proceedings of the 2003 Design, 2003

Exploring regular fabrics to optimize the performance-cost trade-off.
Proceedings of the 40th Design Automation Conference, 2003

2002
Synthesis of Morphable Multipliers.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Simultaneous Optimization of Driving Buffer and Routing Switch Sizes in an FPGA using an Iso-Area Approach.
Proceedings of the 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 2002

Morphable Multipliers.
Proceedings of the Field-Programmable Logic and Applications, 2002

FPGA switch block layout and evaluation.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2002

Queue Machines: Hardware Compilation in Hardware.
Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002

Memory optimization in single chip network switch fabrics.
Proceedings of the 39th Design Automation Conference, 2002

2001
SoC Design Skills: Collaboration Builds a Stronger SoC Design Team.
Proceedings of the 2001 International Conference on Microelectronics Systems Education, 2001

2000
Pipeline Reconfigurable FPGAs.
J. VLSI Signal Process., 2000

PipeRench: A Reconfigurable Architecture and Compiler.
Computer, 2000

PipeRench implementation of the instruction path coprocessor.
Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, 2000

Scalable interconnect and power distribution for island-style FPGAs (poster abstract).
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2000

The John Henry Syndrome (panel session)(abstract only): humans vs. machines as FPGA designers.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2000

Implementation of Near Shannon Limit Error-Correcting Codes Using Reconfigurable Hardware.
Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

1999
Mixed-swing quadrail for low power dual-rail domino logic.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

PipeRench: A Coprocessor for Streaming multimedia Acceleration.
Proceedings of the 26th Annual International Symposium on Computer Architecture, 1999

Extra-Dimensional Island-Style FPGAs.
Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999

PCI-PipeRench and the SWORDAPI: A System for Stream-Based Reconfigurable Computing.
Proceedings of the 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 1999

Vertical Benchmarks for CAD.
Proceedings of the 36th Conference on Design Automation, 1999

1998
Address generation for memories containing multiple arrays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Managing Pipeline-Reconfigurable FPGAs.
Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

Characterization and Parameterization of a Pipeline Reconfigurable FPGA.
Proceedings of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 1998

1997
Synthesis of application-specific memory designs.
IEEE Trans. Very Large Scale Integr. Syst., 1997

Is Reconfigurable Computing Commercially Viable (panel)?
Proceedings of the 1997 ACM/SIGDA Fifth International Symposium on Field Programmable Gate Arrays, 1997

Incremental reconfiguration for pipelined applications.
Proceedings of the 5th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '97), 1997

1995
Array mapping in behavioral synthesis.
Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), 1995

Hidden Markov modeling and fuzzy controllers in FPGAs.
Proceedings of the 3rd IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '95), 1995

1993
A Model and Methodology for Hardware-Software Codesign.
IEEE Des. Test Comput., 1993


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