Sudhakar Yalamanchili

Affiliations:
  • Georgia Institute of Technology, Atlanta, USA


According to our database1, Sudhakar Yalamanchili authored at least 174 papers between 1982 and 2021.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2014, "For contributions to high-performance multiprocessor architecture and communication".

Timeline

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Bibliography

2021
MAHASIM: Machine-Learning Hardware Acceleration Using a Software-Defined Intelligent Memory System.
J. Signal Process. Syst., 2021

Efficiently Solving Partial Differential Equations in a Partially Reconfigurable Specialized Hardware.
IEEE Trans. Computers, 2021

VDPred: Predicting Voltage Droop for Power-Effient 3D Multi-core Processor Design.
Proceedings of the 13th International Conference on Computer and Automation Engineering, 2021

2020
ALRESCHA: A Lightweight Reconfigurable Sparse-Computation Accelerator.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

Tango: An Optimizing Compiler for Just-In-Time RTL Simulation.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
ERIDANUS: Efficiently Running Inference of DNNs Using Systolic Arrays.
IEEE Micro, 2019

Heterogeneous integration for artificial intelligence: Challenges and opportunities.
IBM J. Res. Dev., 2019

LODESTAR: Creating Locally-Dense CNNs for Efficient Inference on Systolic Arrays.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

POSTER: Tango: An Optimizing Compiler for Just-In-Time RTL Simulation.
Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques, 2019

2018
DeepTrain: A Programmable Embedded Platform for Training Deep Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Instruction-throughput regulation in computer processors with data-center applications.
Discret. Event Dyn. Syst., 2018

TRINITY: Coordinated Performance, Energy and Temperature Management in 3D Processor-Memory Stacks.
CoRR, 2018

Memory Slices: A Modular Building Block for Scalable, Intelligent Memory Systems.
CoRR, 2018

A ferroelectric FET based power-efficient architecture for data-intensive computing.
Proceedings of the International Conference on Computer-Aided Design, 2018

Slim NoC: A Low-Diameter On-Chip Network Topology for High Energy Efficiency and Scalability.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

2017
NeuroTrainer: An Intelligent Memory Module for Deep Learning Training.
CoRR, 2017

Power Regulation in High Performance Multicore Processors.
CoRR, 2017

Pagevault: securing off-chip memory using page-based authentication.
Proceedings of the International Symposium on Memory Systems, 2017

Lightweight SIMT core designs for intelligent 3D stacked DRAM.
Proceedings of the International Symposium on Memory Systems, 2017

Demystifying the characteristics of 3D-stacked memories: A case study for Hybrid Memory Cube.
Proceedings of the 2017 IEEE International Symposium on Workload Characterization, 2017

Application-Specific Performance-Aware Energy Optimization on Android Mobile Devices.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

Power regulation in high performance multicore processors.
Proceedings of the 56th IEEE Annual Conference on Decision and Control, 2017

2016
FNM: An Enhanced Null-Message Algorithm for Parallel Simulation of Multicore Systems.
ACM Trans. Model. Comput. Simul., 2016

Thermally Adaptive Cache Access Mechanisms for 3D Many-Core Architectures.
IEEE Comput. Archit. Lett., 2016

IPA in the loop: Control design for throughput regulation in computer processors.
Proceedings of the 13th International Workshop on Discrete Event Systems, 2016

Power-Constrained Performance Scheduling of Data Parallel Tasks.
Proceedings of the 4th International Workshop on Energy Efficient Supercomputing, 2016

General-purpose join algorithms for large graph triangle listing on heterogeneous systems.
Proceedings of the 9th Annual Workshop on General Purpose Processing using Graphics Processing Unit, 2016

Understanding the Impact of Air and Microfluidics Cooling on Performance of 3D Stacked Memory Systems.
Proceedings of the Second International Symposium on Memory Systems, 2016

LaPerm: Locality Aware Scheduler for Dynamic Parallelism on GPUs.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

Neurocube: A Programmable Digital Neuromorphic Architecture with High-Density 3D Memory.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

Amdahl's law for lifetime reliability scaling in heterogeneous multicore processors.
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

2015
Architectural Reliability: Lifetime Reliability Characterization and Management ofMany-Core Processors.
IEEE Comput. Archit. Lett., 2015

Understanding Energy Aspects of Processing-near-Memory for HPC Workloads.
Proceedings of the 2015 International Symposium on Memory Systems, 2015

SIMT-based Logic Layers for Stacked DRAM Architectures: A Prototype.
Proceedings of the 2015 International Symposium on Memory Systems, 2015

Near Data Processing: Impact and Optimization of 3D Memory System Architecture on the Uncore.
Proceedings of the 2015 International Symposium on Memory Systems, 2015

Dynamic thread block launch: a lightweight execution mechanism to support irregular applications on GPUs.
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

Harmonia: balancing compute and memory power in high-performance GPUs.
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

Managing performance-reliability tradeoffs in multicore processors.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

Application Modeling for Scalable Simulation of Massively Parallel Systems.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

Throughput Regulation in Shared Memory Multicore Processors.
Proceedings of the 22nd IEEE International Conference on High Performance Computing, 2015

Temperature regulation in multicore processors using adjustable-gain integral controllers.
Proceedings of the 2015 IEEE Conference on Control Applications, 2015

2014
Control Principles and On-Chip Circuits for Active Cooling Using Integrated Superlattice-Based Thin-Film Thermoelectric Devices.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Power Modeling for GPU Architectures Using McPAT.
ACM Trans. Design Autom. Electr. Syst., 2014

Coordinated energy management in heterogeneous processors.
Sci. Program., 2014

Co-design of multicore architectures and microfluidic cooling for 3D stacked ICs.
Microelectron. J., 2014

Multipredicate Join Algorithms for Accelerating Relational Graph Processing on GPUs.
Proceedings of the International Workshop on Accelerating Data Management Systems Using Modern Processor and Storage Architectures, 2014

An efficient front-end for timing-directed parallel simulation of multi-core system.
Proceedings of the 7th International ICST Conference on Simulation Tools and Techniques, 2014

Architecture-independent modeling of intra-node data movement.
Proceedings of the 2014 LLVM Compiler Infrastructure in HPC, 2014

Bubble sharing: Area and energy efficient adaptive routers using centralized buffers.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

Manifold: A parallel simulation framework for multicore systems.
Proceedings of the 2014 IEEE International Symposium on Performance Analysis of Systems and Software, 2014

Energy Introspector: A parallel, composable framework for integrated power-reliability-thermal modeling for multicore architectures.
Proceedings of the 2014 IEEE International Symposium on Performance Analysis of Systems and Software, 2014

Characterization and analysis of dynamic parallelism in unstructured GPU applications.
Proceedings of the 2014 IEEE International Symposium on Workload Characterization, 2014

Harmonica: An FPGA-Based Data Parallel Soft Core.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

Red Fox: An Execution Environment for Relational Query Processing on GPUs.
Proceedings of the 12th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2014

ParallelJS: An Execution Framework for JavaScript on Heterogeneous Systems.
Proceedings of the Seventh Workshop on General Purpose Processing Using GPUs, 2014

Efficient Instrumentation of GPGPU Applications Using Information Flow Analysis and Symbolic Execution.
Proceedings of the Seventh Workshop on General Purpose Processing Using GPUs, 2014

2013
Adaptive virtual channel partitioning for network-on-chip in heterogeneous architectures.
ACM Trans. Design Autom. Electr. Syst., 2013

Design space exploration of on-chip ring interconnection for a CPU-GPU heterogeneous architecture.
J. Parallel Distributed Comput., 2013

Relational algorithms for multi-bulk-synchronous processors.
Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2013

Optimizing parallel simulation of multicore systems using domain-specific knowledge.
Proceedings of the SIGSIM Principles of Advanced Discrete Simulation, 2013

Centralized buffer router: A low latency, low power router for high radix NOCs.
Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013

A Study of the Effect of Partitioning on Parallel Simulation of Multicore Systems.
Proceedings of the 2013 IEEE 21st International Symposium on Modelling, 2013

Cooperative boosting: needy versus greedy power management.
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

Oncilla: A GAS runtime for efficient resource allocation and data movement in accelerated clusters.
Proceedings of the 2013 IEEE International Conference on Cluster Computing, 2013

Accelerating simulation of agent-based models on heterogeneous architectures.
Proceedings of the 6th Workshop on General Purpose Processor Using Graphics Processing Units, 2013

2012
Characterization and transformation of unstructured control flow in bulk synchronous GPU applications.
Int. J. High Perform. Comput. Appl., 2012

Instruction-based energy estimation methodology for asymmetric manycore processor simulations.
Proceedings of the International ICST Conference on Simulation Tools and Techniques, 2012

Satisfying Data-Intensive Queries Using GPU Clusters.
Proceedings of the 2012 SC Companion: High Performance Computing, 2012

Designing Configurable, Modifiable and Reusable Components for Simulation of Multicore Systems.
Proceedings of the 2012 SC Companion: High Performance Computing, 2012

A universal parallel front-end for execution driven microarchitecture simulation.
Proceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2012

Kernel Weaver: Automatically Fusing Database Primitives for Efficient GPU Computation.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

Lynx: A dynamic instrumentation system for data-parallel applications on GPGPU architectures.
Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2012

Optimizing Data Warehousing Applications for GPUs Using Kernel Fusion/Fission.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

Performance impact of virtual machine placement in a datacenter.
Proceedings of the 31st IEEE International Performance Computing and Communications Conference, 2012

Commodity Converged Fabrics for Global Address Spaces in Accelerator Clouds.
Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012

Eiger: A framework for the automated synthesis of statistical performance models.
Proceedings of the 19th International Conference on High Performance Computing, 2012

Dynamic compilation of data-parallel kernels for vector processors.
Proceedings of the 10th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2012

Throughput regulation in multicore processors via IPA.
Proceedings of the 51th IEEE Conference on Decision and Control, 2012

A power capping controller for multicore processors.
Proceedings of the American Control Conference, 2012

2011
Switching Techniques.
Proceedings of the Encyclopedia of Parallel Computing, 2011

Interconnection Networks.
Proceedings of the Encyclopedia of Parallel Computing, 2011

A Scalable Design Methodology for Energy Minimization of STTRAM: A Circuit and Architecture Perspective.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Keeneland: Bringing Heterogeneous GPU Computing to the Computational Science Community.
Comput. Sci. Eng., 2011

SIMD re-convergence at thread frontiers.
Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011

A framework for dynamically instrumenting GPU compute applications within GPU Ocelot.
Proceedings of 4th Workshop on General Purpose Processing on Graphics Processing Units, 2011

Regulating Locality vs. Parallelism Tradeoffs in Multiple Memory Controller Environments.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2010
An energy efficient cache design using spin torque transfer (STT) RAM.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Speculative execution on multi-GPU systems.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Controller design for tracking induced miss-rates in cache memories.
Proceedings of the 8th IEEE International Conference on Control and Automation, 2010

Dynamic Partitioned Global Address Spaces for power efficient DRAM virtualization.
Proceedings of the International Green Computing Conference 2010, 2010

Modeling GPU-CPU workloads and systems.
Proceedings of 3rd Workshop on General Purpose Processing on Graphics Processing Units, 2010

HyVM - Hybrid Virtual Machines - Efficient Use of Future Heterogeneous Chip Multiprocessors.
Proceedings of the Architecture of Computing Systems, 2010

Ocelot: a dynamic optimization framework for bulk-synchronous applications in heterogeneous systems.
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

2009
High Performance Non-blocking Switch Design in 3D Die-Stacking Technology.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

A characterization and analysis of PTX kernels.
Proceedings of the 2009 IEEE International Symposium on Workload Characterization, 2009

A methodology for robust, energy efficient design of Spin-Torque-Transfer RAM arrays at scaled technologies.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

2008
Harmony: an execution model and runtime for heterogeneous many core systems.
Proceedings of the 17th International Symposium on High-Performance Distributed Computing (HPDC-17 2008), 2008

An Utilization Driven Framework for Energy Efficient Caches.
Proceedings of the High Performance Computing, 2008

ShareStreams-V: A Virtualized QoS Packet Scheduling Accelerator.
Proceedings of the 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, 2008

2007
Improving cache efficiency via resizing + remapping.
Proceedings of the 25th International Conference on Computer Design, 2007

Customized Placement for High Performance Embedded Processor Caches.
Proceedings of the Architecture of Computing Systems, 2007

2006
Data trace cache: an application specific cache architecture.
SIGARCH Comput. Archit. News, 2006

MMR: A MultiMedia Router architecture to support hybrid workloads.
J. Parallel Distributed Comput., 2006

Customizable Fault Tolerant Caches for Embedded Processors.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

2005
Traffic Scheduling Solutions with QoS Support for an Input-Buffered MultiMedia Router.
IEEE Trans. Parallel Distributed Syst., 2005

2004
ShareStreams: A Scalable Architecture and Hardware Support for High-Speed QoS Packet Schedulers.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

A Framework for Compiler Driven Design Space Exploration for Embedded System Customization.
Proceedings of the Advances in Computer Science, 2004

2003
A Hardware Approach to QoS Support in Cluster Environments: The Multimedia Router MMR.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2003

Leveraging Block Decisions and Aggregation in the ShareStreams QoS Architecture.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

A Solution for Handling Hybrid Traffic in Clustered Environments: The MultiMedia Router MMR.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

2002
A Tunable Communications Library for Data Injection.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2002

Investigating Switch Scheduling Algorithms to Support QoS in the Multimedia Router.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

A multimedia router architecture to provide high performance and QoS guarantees to mixed traffic.
Proceedings of the 2002 IEEE International Conference on Multimedia and Expo, 2002

Architecture and Hardware for Scheduling Gigabit Packet Streams.
Proceedings of the 10th Annual IEEE Symposium on High Performance Interconnects (HOTIC 2002), August 21, 2002

The Customization Landscape for Embedded Systems.
Proceedings of the High Performance Computing, 2002

Algorithms for Switch-Scheduling in the Multimedia Router for LANs.
Proceedings of the High Performance Computing, 2002

A new switch scheduling algorithm to improve QoS in the multimedia router.
Proceedings of the IEEE 5th Workshop on Multimedia Signal Processing, 2002

2001
Tuning Buffer Size in the Multimedia Router (MMR).
Proceedings of the 15th International Parallel & Distributed Processing Symposium (IPDPS-01), 2001

A Cost-Effective Hardware Link Scheduling Algorithm for the Multimedia Router (MMR).
Proceedings of the Networking, 2001

2000
Configurable Algorithms for Complete Exchange in 2D Meshes.
IEEE Trans. Parallel Distributed Syst., 2000

Software-Based Rerouting for Fault-Tolerant Pipelined Communication.
IEEE Trans. Parallel Distributed Syst., 2000

An Extensible Message Layer for High-Performance Clusters.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000

Switch Scheduling in the Multimedia Router (MMR).
Proceedings of the 14th International Parallel & Distributed Processing Symposium (IPDPS'00), 2000

1999
Dynamically Configurable Message Flow Control for Fault-Tolerant Routing.
IEEE Trans. Parallel Distributed Syst., 1999

Teaching Pipelining and Concurrency using Hardware Description Languages.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 1999

MMR: A High-Performance Multimedia Router - Architecture and Design Trade-Offs.
Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, 1999

QUIC: A Quality of Service Network Interface Layer for Communication in NOWs.
Proceedings of the 8th Heterogeneous Computing Workshop, 1999

Performance Evaluation of the Multimedia Router with MPEG-2 Video Traffic.
Proceedings of the Network-Based Parallel Computing: Communication, 1999

1998
All-To-All Communication with Minimum Start-Up Costs in 2D/3D Tori and Meshes.
IEEE Trans. Parallel Distributed Syst., 1998

FARA - A Framework for Adaptive Resource Allocation in Complex Real-Time Systems.
Proceedings of the Fourth IEEE Real-Time Technology and Applications Symposium, 1998

1997
On adaptive resource allocation for complex real-time application.
Proceedings of the 18th IEEE Real-Time Systems Symposium (RTSS '97), 1997

Power/Performance Trade-offs for Direct Networks.
Proceedings of the Parallel Computer Routing and Communication, 1997

Deadlock- and Livelock-Free Routing Protocols for Wave Switching.
Proceedings of the 11th International Parallel Processing Symposium (IPPS '97), 1997

Power Constrained Design of Multiprocessor Interconnection Networks.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

Architectural Support for Reducing Communication Overhead in Multiprocessor Interconnection Networks.
Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture (HPCA '97), 1997

Interconnection networks - an engineering approach.
IEEE, ISBN: 978-0-8186-7800-4, 1997

1996
Augmented Binary Hypercube: A New Architecture for Processor Management.
IEEE Trans. Computers, 1996

Distributed Deadlock-Free Routing in Faulty, Pipelined, Direct Interconnection Networks.
IEEE Trans. Computers, 1996

Paradigms for Modeling and Simulation of Multiprocessor Architectures.
Int. J. Comput. Simul., 1996

Using rapid prototyping in computer architecture design laboratories.
Proceedings of the 1996 workshop on Computer architecture education, 1996

Optimistic parallel computation: an example from computational chemistry.
Proceedings of the Eighth IEEE Symposium on Parallel and Distributed Processing, 1996

Algorithms for All-to-All Personalized Exchange in 2D and 3D Tori.
Proceedings of IPPS '96, 1996

A High Performance Router Architecture for Interconnection Networks.
Proceedings of the 1996 International Conference on Parallel Processing, 1996

Adaptive resource allocation for embedded parallel applications.
Proceedings of the 3rd International Conference on High Performance Computing, 1996

Incorporating Multi-Chip Module Packaging Constraints into System Design.
Proceedings of the 1996 European Design and Test Conference, 1996

1995
A Family of Fault-Tolerant Routing Protocols for Direct Multiprocessor Networks.
IEEE Trans. Parallel Distributed Syst., 1995

Parallelism in Sequential Multiprocessor Simulation Models: A Case Study.
ACM Trans. Model. Comput. Simul., 1995

A Performance Model of Pipelined K-ary n-cubes.
IEEE Trans. Computers, 1995

Partitioning and mapping in embedded multiprocessor architectures in the presence of constraints.
Concurr. Pract. Exp., 1995

Configurable Flow Control Mechanisms for Fault-Tolerant Routing.
Proceedings of the 22nd Annual International Symposium on Computer Architecture, 1995

Time scale combining of conservative parallel discrete event simulations.
Proceedings of IPPS '95, 1995

Software Based Fault-Tolerant Oblivious Routing in Pipelined Networks.
Proceedings of the 1995 International Conference on Parallel Processing, 1995

1994
Large Join Optimization on a Hypercube Multiprocessor.
IEEE Trans. Knowl. Data Eng., 1994

Partitioning Coarse-Grain Signal Flow Graphs for Heterogeneous DSP Architectures.
Int. J. Comput. Simul., 1994

Simulation of Marked Graphs on SIMD Architectures Using Efficient Memory Management.
Proceedings of the MASCOTS '94, Proceedings of the Second International Workshop on Modeling, Analysis, and Simulation On Computer and Telecommunication Systems, January 31, 1994

Ariadne - An Adaptive Router for Fault-Tolerant Multicomputers.
Proceedings of the 21st Annual International Symposium on Computer Architecture. Chicago, 1994

Scouting: Fully Adaptive, Deadlock-Free Routing in Faulty Pipelined Networks.
Proceedings of the Proceedings 1994 International Conference on Parallel and Distributed Systems, 1994

1993
Adaptive Routing Protocols for Hypercube Interconnection Networks.
Computer, 1993

Genie: An Environment for Partitioning and Mapping in Embedded Multiprocessors.
Proceedings of the Fifth IEEE Symposium on Parallel and Distributed Processing, 1993

Partitioning and Mapping a Class of Parallel Multiprocessor Simulation Models.
Proceedings of the Fifth IEEE Symposium on Parallel and Distributed Processing, 1993

Analytical Models of Bandwidth Allocation in Pipelined <i>k</i>-ary <i>n</i>-cubes.
Proceedings of the Seventh International Parallel Processing Symposium, 1993

1992
Pipelined Circuit-Switching: A Fault-Tolerant Variant of Wormhole Routing.
Proceedings of the Fourth IEEE Symposium on Parallel and Distributed Processing, 1992

Dominant Representations: A Paradigm for Mapping Parallel Computations.
Proceedings of the 6th International Parallel Processing Symposium, 1992

Parallel Optimization and Execution of Large Join Queries.
Proceedings of the International Conference on Fifth Generation Computer Systems. FGCS 1992, 1992

1991
Adaptive routing in generalized hypercube architectures.
Proceedings of the Third IEEE Symposium on Parallel and Distributed Processing, 1991

1987
A Characterization and Analysis of Parallel Processor Interconnection Networks.
IEEE Trans. Computers, 1987

Parallel image normalization on a mesh connected array processor.
Pattern Recognit., 1987

1985
A system organization for parallel image processing.
Pattern Recognit., 1985

Analysis of a model for parallel image processing.
Pattern Recognit., 1985

Reconfiguration Strategies for Parallel Architectures.
Computer, 1985

1984
Formulation of parallel image processing tasks.
Pattern Recognit. Lett., 1984

Workstations in a Local Area Network Environment.
Computer, 1984

Algebraic Properties of some Parallel Processor Interconnection Networks.
Proceedings of the First International Conference on Data Engineering, 1984

1982
Extraction of moving object descriptions via differencing.
Comput. Graph. Image Process., 1982


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