Stefano Di Francescantonio

According to our database, Stefano Di Francescantonio authored at least 7 papers between 2001 and 2004.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2004

Implications of Clock Distribution Faults and Issues with Screening Them during Manufacturing Testing.

Cecilia Metra, Stefano Di Francescantonio, T. M. Mak

IEEE Trans. Computers, 2004

2003

Scan flip-flops with on-line testing ability with respect to input delay and crosstalk faults.

Cecilia Metra, Stefano Di Francescantonio, Michele Favalli, Bruno Riccò

Microelectron. J., 2003

Automatic Modification of Sequential Circuits for Self-Checking Implementation.

Cecilia Metra, Stefano Di Francescantonio, Martin Omaña

Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

2002

On-Chip Clock Faults' Detector.

Cecilia Metra, Michele Favalli, Stefano Di Francescantonio, Bruno Riccò

J. Electron. Test., 2002

Clock Faults? Impact on Manufacturing Testing and Their Possible Detection Through On-Line Testing.

Cecilia Metra, Stefano Di Francescantonio, T. M. Mak

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

On-Line Testing of Transient Faults Affecting Functional Blocks of FCMOS, Domino and FPGA-Implemented Self-Checking Circuits.

Cecilia Metra, Stefano Di Francescantonio, Giuseppe Marrale

Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

2001

Evaluation of Clock Distribution Networks' Most Likely Faults and Produced Effects.

Cecilia Metra, Stefano Di Francescantonio, Bruno Riccò, T. M. Mak

Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001