Bruno Riccò

According to our database1, Bruno Riccò authored at least 103 papers between 1988 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2003, "For contributions to thin oxide MOS devices and non volatile memories.".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
Practical Determination of Solid Fat Content in Fats and Oils by Single-Wavelength Near-Infrared Analysis.
IEEE Trans. Instrumentation and Measurement, 2020

2019
Computer Vision Approach for the Determination of Microbial Concentration and Growth Kinetics Using a Low Cost Sensor System.
Sensors, 2019

2017
Bacterial concentration detection using a portable embedded sensor system for environmental monitoring.
Proceedings of the 7th IEEE International Workshop on Advances in Sensors and Interfaces, 2017

2016
GLOVR: a wearable hand controller for virtual reality applications.
Proceedings of the 2016 Virtual Reality International Conference, 2016

2014
A novel electrochemical method for olive oil acidity determination.
Microelectron. J., 2014

2013
Augmented graphics for interactive storytelling on a mobile device.
Proceedings of the SIGGRAPH Asia 2013 Symposium on Mobile Graphics and Interactive Applications, 2013

BRAVO: a brain virtual operator for education exploiting brain-computer interfaces.
Proceedings of the 2013 ACM SIGCHI Conference on Human Factors in Computing Systems, 2013

2010
Aware and smart environments: The Casattenta project.
Microelectron. J., 2010

Capacitance DNA bio-chips improved by new probe immobilization strategies.
Microelectron. J., 2010

2009
Fault diagnosis and test of DNA sensor arrays by using IFA approach.
Microelectron. J., 2009

Design of an integrated low-noise read-out system for DNA capacitive sensors.
Microelectron. J., 2009

Smart sensors for fast biological analysis.
Microelectron. J., 2009

2008
A smart wireless glove for gesture interaction.
Proceedings of the International Conference on Computer Graphics and Interactive Techniques, 2008

High Resolution Read-Out Circuit for DNA Label-Free Detection System.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

2007
MOCA: A Low-Power, Low-Cost Motion Capture System Based on Integrated Accelerometers.
Adv. in MM, 2007

Inductive Fault Analysis for Test and Diagnosis of DNA Sensor Arrays.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

2006
Linux-Based Data Acquisition and Processing on Palmtop Computer.
IEEE Trans. Instrumentation and Measurement, 2006

Design and characterization of novel read-out systems for a capacitive DNA sensor.
Microelectron. J., 2006

Innovative Optoeletronic Approaches to Biomolecular Analysis with Arrays of Silicon Devices.
Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006

Innovative Optoelectronic Approaches to Biomolecular Analysis with Arrays of Silicon Devices.
Proceedings of the IFIP VLSI-SoC 2006, 2006

Gesture Signature for Ambient Intelligence Applications: A Feasibility Study.
Proceedings of the Pervasive Computing, 2006

3dID: a low-power, low-cost hand motion capture device.
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

2005
Pervasive Computing for Interactive Virtual Heritage.
IEEE MultiMedia, 2005

Design and Implementation of WiMoCA Node for a Body Area Wireless Sensor Network.
Proceedings of the Systems Communications 2005 (ICW / ICHSN / ICMCS / SENET 2005), 2005

Hardware-Software Design of a Smart Sensor for Fully-Electronic DNA Hybridization Detection.
Proceedings of the 2005 Design, 2005

2003
Scan flip-flops with on-line testing ability with respect to input delay and crosstalk faults.
Microelectron. J., 2003

Automatic Repositioning Technique for Digital Cell Based Window Comparators and Implementation within Mixed-Signal DfT Schemes.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

Self-positioning digital window comparators for mixed-signal DfT.
Proceedings of 9th IEEE International Conference on Emerging Technologies and Factory Automation, 2003

2002
Microscopic aspects of defect generation in SiO2.
Microelectron. Reliab., 2002

Digital Window Comparator DfT Scheme for Mixed-Signal ICs.
J. Electronic Testing, 2002

On-Chip Clock Faults' Detector.
J. Electronic Testing, 2002

Power aware network interface management for streaming multimedia.
Proceedings of the 2002 IEEE Wireless Communications and Networking Conference Record, 2002

Fast and Compact Error Correcting Scheme for Reliable Multilevel Flash Memories.
Proceedings of the 10th IEEE International Workshop on Memory Technology, 2002

Testing of Analogue Circuits via (Standard) Digital Gates.
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

Parametric timing and power macromodels for high level simulation of low-swing interconnects.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Energy-efficient and reliable low-swing signaling for on-chip buses based on redundant coding.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

An adaptive data compression scheme for memory traffic minimization in processor-based systems.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Automated DNA sizing in atomic force microscope images.
Proceedings of the 2002 IEEE International Symposium on Biomedical Imaging, 2002

A New Stress Sensor for Force/Torque Measurements.
Proceedings of the 2002 IEEE International Conference on Robotics and Automation, 2002

Self-Checking Scheme for the On-Line Testing of Power Supply Noise.
Proceedings of the 2002 Design, 2002

Low Power Control Techniques For TFT LCD Displays.
Proceedings of the International Conference on Compilers, 2002

System lifetime extension by battery management: an experimental work.
Proceedings of the International Conference on Compilers, 2002

2001
Software-controlled processor speed setting for low-power streamingmultimedia.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Energy characterization of embedded real-time operating systems.
SIGARCH Computer Architecture News, 2001

On-line testing of transient and crosstalk faults affecting interconnections of FPGA-implemented systems.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Evaluation of Clock Distribution Networks' Most Likely Faults and Produced Effects.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

An adaptive algorithm for low-power streaming multimedia processing.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Processor frequency setting for energy minimization of streaming multimedia application.
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001

2000
Signal Coding and CMOS Gates for Combinational Functional Blocks of Very Deep Submicron Self-checking Circuits.
VLSI Design, 2000

Self-Checking Detection and Diagnosis of Transient, Delay, and Crosstalk Faults Affecting Bus Lines.
IEEE Trans. Computers, 2000

On-Line Testing and Diagnosis of Bus Lines with respect to Intermediate Voltage Values.
Proceedings of the 2000 Design, 2000

1999
Self-checking scheme for very fast clocks' skew correction.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Efficient switching activity computation during high-level synthesis of control-dominated designs.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

1998
Concurrent Checking of Clock Signal Correctness.
IEEE Design & Test of Computers, 1998

On-line detection of logic errors due to crosstalk, delay, and transient faults.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Monitoring system activity for OS-directed dynamic power management.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Signal Coding Technique and CMOS Gates for Strongly Fault-Secure Combinational Functional Blocks.
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

Highly Testable and Compact 1-out-of-n Code Checker with Single Output.
Proceedings of the 1998 Design, 1998

1997
Gate-level power and current simulation of CMOS integrated circuits.
IEEE Trans. VLSI Syst., 1997

On-line detection of bridging and delay faults in functional blocks of CMOS self-checking circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

Highly testable and compact single output comparator.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

On-Line Testing Scheme for Clock's Faults.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Compact and low power on-line self-testing voting scheme.
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997

1996
Embedded two-rail checkers with on-line testing ability.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Gate-level current waveform simulation of CMOS integrated circuits.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

Tree Checkers for Applications with Low Power-Delay Requirements.
Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

Compact and Highly Testable Error Indicator for Self-Checking Circuits.
Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

Power Estimation of Cell-Based CMOS Circuits.
Proceedings of the 33st Conference on Design Automation, 1996

1995
Design of CMOS checkers with improved testability of bridging and transistor stuck-on faults.
J. Electronic Testing, 1995

Reliability evaluation of combinational logic circuits by symbolic simulation.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Novel Berger code checker.
Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995

A novel DFT technique for critical bridging faults in CMOS and BiCMOS ICs.
Proceedings of the 1995 European Design and Test Conference, 1995

1994
Modeling of Broken Connections Faults in CMOS ICs.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Highly Testable and Compact 1-out-of-n CMOS Checkers.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994

CMOS Self Checking Circuits with Faulty Sequential Functional Block.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994

1993
Analysis of resistive bridging fault detection in BiCMOS digital ICs.
IEEE Trans. VLSI Syst., 1993

Fault simulation of parametric bridging faults in CMOS IC's.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1993

A numerical method to compute isotropic band models from anisotropic semiconductor band structures.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1993

Analyss of Dynamic Effects of Resistive Bridging Faults in CMOS and BiCMOS Digital ICs.
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

A Highly Testable 1-out-of-3 CMOS Checker.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993

Design Rules for CMOS Self Checking Circuits with Parametric Faults in the Functional Block.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993

1992
A probabilistic fault model for 'analog' faults in digital CMOS circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1992

Testability measures in pseudorandom testing.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1992

Dynamic effects in the detection of bridging faults in CMOS ICs.
J. Electronic Testing, 1992

CMOS Checkers with Testable Bridging and Transistor Stuck-on Faults.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

Analysis of Steady State Detection of Resistive Bridging Faults in BiCMOS Digital ICs.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

Parametric Bridging Fault Characterization for the Fault Simulation of Library-Based ICs.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

1991
Monte Carlo simulations of high energy electrons and holes in Si-n-MOSFET's.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1991

A novel critical path heuristic for fast fault grading.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1991

Fault simulation of unconventional faults in CMOS circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1991

Analysis and Design of Linear Finite State Machines for Signature Analysis Testing.
IEEE Trans. Computers, 1991

Fault simulation for general FCMOS ICs.
J. Electronic Testing, 1991

A probabilistic fault model for analog faults.
Proceedings of the conference on European design automation, 1991

Detection of PLA multiple crosspoint faults.
Proceedings of the conference on European design automation, 1991

1990
Aliasing in signature analysis testing with multiple input shift registers.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1990

Testing of E2PROM aging and endurance: A case study.
European Transactions on Telecommunications, 1990

An improved procedure to test CMOS ICs for latch-up.
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

1989
A general purpose device simulator coupling Poisson and Monte Carlo transport with applications to deep submicron MOSFETs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1989

An analytical model for the aliasing probability in signature analysis testing.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1989

On the Design of Multiple-Input Shift-Registers for Signature Analysis Testing.
Proceedings of the Proceedings International Test Conference 1989, 1989

A Testing Technique to Characterize E^2PROM's Aging and Endurance.
Proceedings of the Proceedings International Test Conference 1989, 1989

CMOS Design for Improved IC Testability.
Proceedings of the Proceedings International Test Conference 1989, 1989

1988
MOS2: an efficient MOnte Carlo Simulator for MOS devices.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1988


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