Michele Favalli

According to our database, Michele Favalli authored at least 90 papers between 1988 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Efficient Resource-Aware Neural Architecture Search with a Neuro-Symbolic Approach.

Elena Bellodi, Davide Bertozzi, Alice Bizzarri, Michele Favalli, Michele Fraccaroli, Riccardo Zese

Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023

2022

Exploring Software Models for the Resilience Analysis of Deep Learning Accelerators: the NVDLA Case Study.

Alessandro Veronesi, Francesco Dall'Occo, Davide Bertozzi, Michele Favalli, Milos Krstic

Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022

2021

The Challenge of Classification Confidence Estimation in Dynamically-Adaptive Neural Networks.

Francesco Dall'Occo, Andrés Bueno-Crespo, José L. Abellán, Davide Bertozzi, Michele Favalli

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2021

2018

A Boolean model for delay fault testing of emerging digital technologies based on ambipolar devices.

Marcello Dalpasso, Davide Bertozzi, Michele Favalli

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2016

Boolean and Pseudo-Boolean Test Generation for Feedback Bridging Faults.

Michele Favalli, Marcello Dalpasso

IEEE Trans. Computers, 2016

A built-in self-testing framework for asynchronous bundled-data NoC switches resilient to delay variations.

Gabriele Miorandi, Alberto Celin, Michele Favalli, Davide Bertozzi

Proceedings of the Tenth IEEE/ACM International Symposium on Networks-on-Chip, 2016

2014

Efficient testing of multi-output combinational cells in nano-complementary metal oxide semiconductor integrated circuits.

L. Valenti, Marcello Dalpasso, Michele Favalli

IET Comput. Digit. Tech., 2014

Applications of Boolean Satisfiability to Verification and Testing of Switch-Level Circuits.

Michele Favalli, Marcello Dalpasso

J. Electron. Test., 2014

2013

A complete self-testing and self-configuring NoC infrastructure for cost-effective MPSoCs.

Alberto Ghiribaldi, Daniele Ludovici, Francisco Triviño, Alessandro Strano, José Flich, José L. Sánchez, Francisco J. Alfaro, Michele Favalli, Davide Bertozzi

ACM Trans. Embed. Comput. Syst., 2013

2012

Power efficiency of switch architecture extensions for fault tolerant NoC design.

Alberto Ghiribaldi, Alessandro Strano, Michele Favalli, Davide Bertozzi

Proceedings of the 2012 International Green Computing Conference, 2012

2011

A SAT Based Test Generation Method for Delay Fault Testing of Macro Based Circuits.

Santino Mele, Michele Favalli

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

System-level infrastructure for boot-time testing and configuration of networks-on-chip with programmable routing logic.

Alberto Ghiribaldi, Daniele Ludovici, Michele Favalli, Davide Bertozzi

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Exploiting Network-on-Chip structural redundancy for a cooperative and scalable built-in self-test architecture.

Alessandro Strano, Crispín Gómez Requena, Daniele Ludovici, Michele Favalli, María Engracia Gómez, Davide Bertozzi

Proceedings of the Design, Automation and Test in Europe, 2011

2009

Testing Resistive Opens and Bridging Faults Through Pulse Propagation.

Michele Favalli, Cecilia Metra

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

How Many Test Vectors We Need to Detect a Bridging Fault?

Michele Favalli, Marcello Dalpasso

J. Electron. Test., 2009

2007

High Quality Test Vectors for Bridging Faults in the Presence of IC's Parameters Variations.

Michele Favalli, Marcello Dalpasso

Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

Delay Fault Detection Problems in Circuits Featuring a Low Combinational Depth.

Michele Favalli

Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

Interactive presentation: Pulse propagation for the detection of small delay defects.

Michele Favalli, Cecilia Metra

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

Diversity Analysis in the Presence of Delay Faults Affecting Duplex Systems.

Michele Favalli

IEEE Trans. Computers, 2006

2005

A fuzzy model for path delay fault detection.

Michele Favalli

IEEE Trans. Very Large Scale Integr. Syst., 2005

2004

TMR voting in the presence of crosstalk faults at the voter inputs.

Michele Favalli, Cecilia Metra

IEEE Trans. Reliab., 2004

Annotated Bit Flip Fault Model.

Michele Favalli

Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

"Victim Gate" Crosstalk Fault Model.

Michele Favalli

Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

2003

Concurrent detection of power supply noise.

Cecilia Metra, Luca Schiano, Michele Favalli

IEEE Trans. Reliab., 2003

Scan flip-flops with on-line testing ability with respect to input delay and crosstalk faults.

Cecilia Metra, Stefano Di Francescantonio, Michele Favalli, Bruno Riccò

Microelectron. J., 2003

2002

Bridging fault modeling and simulation for deep submicron CMOS ICs.

Michele Favalli, Marcello Dalpasso

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

On-Chip Clock Faults' Detector.

Cecilia Metra, Michele Favalli, Stefano Di Francescantonio, Bruno Riccò

J. Electron. Test., 2002

Single Output Distributed Two-Rail Checker with Diagnosing Capabilities for Bus Based Self-Checking Architectures.

Michele Favalli, Cecilia Metra

J. Electron. Test., 2002

Online Testing Approach for Very Deep-Submicron ICs.

Michele Favalli, Cecilia Metra

IEEE Des. Test Comput., 2002

Self-Checking Scheme for the On-Line Testing of Power Supply Noise.

Cecilia Metra, Luca Schiano, Bruno Riccò, Michele Favalli

Proceedings of the 2002 Design, 2002

Problems Due to Open Faults in the Interconnections of Self-Checking Data-Paths.

Michele Favalli, Cecilia Metra

Proceedings of the 2002 Design, 2002

An Evolutionary Approach to the Design of On-Chip Pseudorandom Test Pattern Generators.

Michele Favalli, Marcello Dalpasso

Proceedings of the 2002 Design, 2002

2001

Optimization of error detecting codes for the detection of crosstalk originated errors.

Michele Favalli, Cecilia Metra

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000

Signal Coding and CMOS Gates for Combinational Functional Blocks of Very Deep Submicron Self-checking Circuits.

Cecilia Metra, Michele Favalli, Bruno Riccò

VLSI Design, 2000

Enabling testability of fault-tolerant circuits by means of I_DDQ-checkable voters.

Alessandro Bogliolo, Michele Favalli, Maurizio Damiani

IEEE Trans. Very Large Scale Integr. Syst., 2000

Self-Checking Detection and Diagnosis of Transient, Delay, and Crosstalk Faults Affecting Bus Lines.

Cecilia Metra, Michele Favalli, Bruno Riccò

IEEE Trans. Computers, 2000

Bridging Faults in Pipelined Circuits.

Michele Favalli, Cecilia Metra

J. Electron. Test., 2000

On-Line Testing and Diagnosis of Bus Lines with respect to Intermediate Voltage Values.

Cecilia Metra, Michele Favalli, Bruno Riccò

Proceedings of the 2000 Design, 2000

Virtual Fault Simulation of Distributed IP-Based Designs.

Marcello Dalpasso, Alessandro Bogliolo, Luca Benini, Michele Favalli

Proceedings of the 2000 Design, 2000

1999

Bus crosstalk fault-detection capabilities of error-detecting codes for on-line testing.

Michele Favalli, Cecilia Metra

IEEE Trans. Very Large Scale Integr. Syst., 1999

On the Design of Self-Checking Functional Units Based on Shannon Circuits.

Michele Favalli, Cecilia Metra

Proceedings of the 1999 Design, 1999

1998

Regression Models for Behavioral Power Estimation.

Luca Benini, Alessandro Bogliolo, Michele Favalli, Giovanni De Micheli

Integr. Comput. Aided Eng., 1998

Concurrent Checking of Clock Signal Correctness.

Cecilia Metra, Michele Favalli, Bruno Riccò

IEEE Des. Test Comput., 1998

On-line detection of logic errors due to crosstalk, delay, and transient faults.

Cecilia Metra, Michele Favalli, Bruno Riccò

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Signal Coding Technique and CMOS Gates for Strongly Fault-Secure Combinational Functional Blocks.

Cecilia Metra, Michele Favalli, Bruno Riccò

Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

Highly Testable and Compact 1-out-of-n Code Checker with Single Output.

Cecilia Metra, Michele Favalli, Bruno Riccò

Proceedings of the 1998 Design, 1998

1997

On-line detection of bridging and delay faults in functional blocks of CMOS self-checking circuits.

Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

A method for increasing the I_DDQ testability.

Marcello Dalpasso, Michele Favalli

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Symbolic Handling of Bridging Fault Effects.

Michele Favalli, Marcello Dalpasso

J. Electron. Test., 1997

Highly testable and compact single output comparator.

Cecilia Metra, Michele Favalli, Bruno Riccò

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

On-Line Testing Scheme for Clock's Faults.

Cecilia Metra, Michele Favalli, Bruno Riccò

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Compact and low power on-line self-testing voting scheme.

Cecilia Metra, Michele Favalli, Bruno Riccò

Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997

Low-level error recovery mechanism for self-checking sequential circuits.

Michele Favalli, Cecilia Metra

Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997

Testing scheme for IC's clocks.

Michele Favalli, Cecilia Metra

Proceedings of the European Design and Test Conference, 1997

1996

Sensing circuit for on-line detection of delay faults.

Michele Favalli, Cecilia Metra

IEEE Trans. Very Large Scale Integr. Syst., 1996

Modeling and simulation of broken connections in CMOS IC's.

Michele Favalli, Marcello Dalpasso, Piero Olivo

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Embedded two-rail checkers with on-line testing ability.

Cecilia Metra, Michele Favalli, Bruno Riccò

Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Tree Checkers for Applications with Low Power-Delay Requirements.

Cecilia Metra, Michele Favalli, Bruno Riccò

Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

Compact and Highly Testable Error Indicator for Self-Checking Circuits.

Cecilia Metra, Michele Favalli, Bruno Riccò

Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

Design for Testability of Gated-Clock FSMs.

Michele Favalli, Luca Benini, Giovanni De Micheli

Proceedings of the 1996 European Design and Test Conference, 1996

1995

Design of CMOS checkers with improved testability of bridging and transistor stuck-on faults.

Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò

J. Electron. Test., 1995

Test pattern generation for I_DDQ: increasing test quality.

Marcello Dalpasso, Michele Favalli, Piero Olivo

Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Analysis of glitch power dissipation in CMOS ICs.

Michele Favalli, Luca Benini

Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995

Novel Berger code checker.

Cecilia Metra, Michele Favalli, Bruno Riccò

Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995

A novel DFT technique for critical bridging faults in CMOS and BiCMOS ICs.

Michele Favalli, Bruno Riccò, L. Penza

Proceedings of the 1995 European Design and Test Conference, 1995

Correlation between I_DDQ testing quality and sensor accuracy.

Marcello Dalpasso, Michele Favalli, Piero Olivo

Proceedings of the 1995 European Design and Test Conference, 1995

1994

Modeling of Broken Connections Faults in CMOS ICs.

Michele Favalli, Marcello Dalpasso, Piero Olivo, Bruno Riccò

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Highly Testable and Compact 1-out-of-n CMOS Checkers.

Cecilia Metra, Michele Favalli, Bruno Riccò

Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994

CMOS Self Checking Circuits with Faulty Sequential Functional Block.

Cecilia Metra, Michele Favalli, Bruno Riccò

Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994

1993

Analysis of resistive bridging fault detection in BiCMOS digital ICs.

Michele Favalli, Marcello Dalpasso, Piero Olivo, Bruno Riccò

IEEE Trans. Very Large Scale Integr. Syst., 1993

Fault simulation of parametric bridging faults in CMOS IC's.

Marcello Dalpasso, Michele Favalli, Piero Olivo, Bruno Riccò

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Analyss of Dynamic Effects of Resistive Bridging Faults in CMOS and BiCMOS Digital ICs.

Michele Favalli, Marcello Dalpasso, Piero Olivo, Bruno Riccò

Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

A Highly Testable 1-out-of-3 CMOS Checker.

Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò

Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993

Design Rules for CMOS Self Checking Circuits with Parametric Faults in the Functional Block.

Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò

Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993

1992

A probabilistic fault model for 'analog' faults in digital CMOS circuits.

Michele Favalli, Piero Olivo, Bruno Riccò

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Testability measures in pseudorandom testing.

Silvia Ercolani, Michele Favalli, Maurizio Damiani, Piero Olivo, Bruno Riccò

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Dynamic effects in the detection of bridging faults in CMOS ICs.

Michele Favalli, Piero Olivo, Bruno Riccò

J. Electron. Test., 1992

CMOS Checkers with Testable Bridging and Transistor Stuck-on Faults.

Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò

Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

Analysis of Steady State Detection of Resistive Bridging Faults in BiCMOS Digital ICs.

Michele Favalli, Marcello Dalpasso, Piero Olivo, Bruno Riccò

Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

Parametric Bridging Fault Characterization for the Fault Simulation of Library-Based ICs.

Marcello Dalpasso, Michele Favalli, Piero Olivo, Bruno Riccò

Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

1991

A novel critical path heuristic for fast fault grading.

Michele Favalli, Piero Olivo, Bruno Riccò

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Fault simulation of unconventional faults in CMOS circuits.

Michele Favalli, Piero Olivo, Maurizio Damiani, Bruno Riccò

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Fault simulation for general FCMOS ICs.

Michele Favalli, Piero Olivo, Bruno Riccò, Fabio Somenzi

J. Electron. Test., 1991

A probabilistic fault model for analog faults.

Michele Favalli, Piero Olivo, Bruno Riccò

Proceedings of the conference on European design automation, 1991

Detection of PLA multiple crosspoint faults.

M. Ambanelli, Michele Favalli, Piero Olivo, Bruno Riccò

Proceedings of the conference on European design automation, 1991

1990

Aliasing in signature analysis testing with multiple input shift registers.

Maurizio Damiani, Piero Olivo, Michele Favalli, Silvia Ercolani, Bruno Riccò

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

1989

An analytical model for the aliasing probability in signature analysis testing.

Maurizio Damiani, Piero Olivo, Michele Favalli, Bruno Riccò

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

CMOS Design for Improved IC Testability.

Michele Favalli, Piero Olivo, Maurizio Damiani, Bruno Riccò

Proceedings of the Proceedings International Test Conference 1989, 1989

Improved testability evaluations in combinational logic networks.

Silvia Ercolani, Michele Favalli, Maurizio Damiani, Piero Olivo, Bruno Riccò

Proceedings of the Computer Design: VLSI in Computers and Processors, 1989

1988

Aliasing errors in signature analysis testing of integrated circuits.

Maurizio Damiani, Piero Olivo, Michele Favalli, Bruno Riccò

Proceedings of the Computer Design: VLSI in Computers and Processors, 1988