Steven G. Rothweiler

According to our database1, Steven G. Rothweiler authored at least 9 papers between 1988 and 1997.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

1997
Redundancy removal and test generation for circuits with non-Boolean primitives.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Deriving Signal Constraints to Accelerate Sequential Test Generation.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

1995
Redundancy Removal and Test Generation for Circuits with Non-Boolean Primitives.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

1993
A transitive closure algorithm for test generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Sequential Circuit Delay optimization Using Global Path Delays.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992
Performance optimization of sequential circuits by eliminating retiming bottlenecks.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

1989
Mind: a module binder for high level synthesis.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1989

1988
BECOME: Behavior Level Circuit Synthesis Based on Structure Mapping.
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

Bridge: A Versatile Behavioral Synthesis System.
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988


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