Vijay Gangaram

According to our database, Vijay Gangaram authored at least 14 papers between 1995 and 2018.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2018

Online Scan Diagnosis : A Novel Approach to Volume Diagnosis.

I-De Huang, Pallav Gupta, Loganathan Lingappan, Vijay Gangaram

Proceedings of the IEEE International Test Conference, 2018

2013

Test generation for circuits with embedded memories using SMT.

Sarvesh Prabhu, Michael S. Hsiao, Loganathan Lingappan, Vijay Gangaram

Proceedings of the 18th IEEE European Test Symposium, 2013

2012

A SMT-based diagnostic test generation method for combinational circuits.

Sarvesh Prabhu, Michael S. Hsiao, Loganathan Lingappan, Vijay Gangaram

Proceedings of the 30th IEEE VLSI Test Symposium, 2012

A Novel SMT-Based Technique for LFSR Reseeding.

Sarvesh Prabhu, Michael S. Hsiao, Loganathan Lingappan, Vijay Gangaram

Proceedings of the 25th International Conference on VLSI Design, 2012

2011

An Efficient 2-Phase Strategy to Achieve High Branch Coverage.

Sarvesh Prabhu, Michael S. Hsiao, Saparya Krishnamoorthy, Loganathan Lingappan, Vijay Gangaram, Jim Grundy

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2009

Fast Enhancement of Validation Test Sets for Improving the Stuck-at Fault Coverage of RTL Circuits.

Loganathan Lingappan, Vijay Gangaram, Niraj K. Jha, Sreejit Chakravarty

IEEE Trans. Very Large Scale Integr. Syst., 2009

2008

Efficient Selection of Observation Points for Functional Tests.

Jian Kang, Sharad C. Seth, Yi-Shing Chang, Vijay Gangaram

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

2007

Efficient RTL Coverage Metric for Functional Test Selection.

Jian Kang, Sharad C. Seth, Vijay Gangaram

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Fast Enhancement of Validation Test Sets to Improve Stuck-at Fault Coverage for RTL circuits.

Loganathan Lingappan, Vijay Gangaram, Niraj K. Jha

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

2006

Upper Bounding Fault Coverage by Structural Analysis and Signal Monitoring.

Vishwani D. Agrawal, Soumitra Bose, Vijay Gangaram

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Functional Test Selection for High Volume Manufacturing.

Vijay Gangaram, Deepa Bhan, James K. Caldwell

Proceedings of the Seventh International Workshop on Microprocessor Test and Verification (MTV 2006), 2006

1998

A controller redesign technique to enhance testability of controller-data path circuits.

Sujit Dey, Vijay Gangaram, Miodrag Potkonjak

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

1997

Deriving Signal Constraints to Accelerate Sequential Test Generation.

Srimat T. Chakradhar, Vijay Gangaram, Steven G. Rothweiler

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

1995

A controller-based design-for-testability technique for controller-data path circuits.

Sujit Dey, Vijay Gangaram, Miodrag Potkonjak

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995