Sudipta Paria

According to our database, Sudipta Paria authored at least 18 papers between 2014 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

POLARIS: Explainable Artificial Intelligence for Mitigating Power Side-Channel Leakage.

Tanzim Mahfuz, Sudipta Paria, Tasneem Suha, Swarup Bhunia, Prabuddha Chakraborty

CoRR, July, 2025

LASA: Enhancing SoC Security Verification with LLM-Aided Property Generation.

Dinesh Reddy Ankireddy, Sudipta Paria, Aritra Dasgupta, Sandip Ray, Swarup Bhunia

CoRR, June, 2025

Enhancing Test Efficiency through Automated ATPG-Aware Lightweight Scan Instrumentation.

Sudipta Paria, Md Rezoan Ferdous, Aritra Dasgupta, Atri Chatterjee, Swarup Bhunia

CoRR, May, 2025

SynFuzz: Leveraging Fuzzing of Netlist to Detect Synthesis Bugs.

Raghul Saravanan, Sudipta Paria, Aritra Dasgupta, Venkat Nitin Patnala, Swarup Bhunia, Sai Manoj PD

CoRR, April, 2025

Library-Attack: Reverse Engineering Approach for Evaluating Hardware IP Protection.

Aritra Dasgupta, Sudipta Paria, Christopher Sozio, Andrew Lukefahr, Swarup Bhunia

CoRR, January, 2025

HIPR: Hardware IP Protection through Low-Overhead Fine-Grain Redaction.

Aritra Dasgupta, Sudipta Paria, Swarup Bhunia

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2025

Towards Automated Verification of IP and COTS: Leveraging LLMs in Pre- and Post-Silicon Stages.

Sudipta Paria, Aritra Dasgupta, Swarup Bhunia

Proceedings of the 43rd IEEE VLSI Test Symposium, 2025

CLIP: A Structural Approach to Cut Points Matching for Logic Equivalence Checking.

Dinesh Reddy Ankireddy, Sudipta Paria, Aritra Dasgupta, Sandip Ray, Swarup Bhunia

Proceedings of the 43rd IEEE VLSI Test Symposium, 2025

2024

SPELL: An End-to-End Tool Flow for LLM-Guided Secure SoC Design for Embedded Systems.

Sudipta Paria, Aritra Dasgupta, Swarup Bhunia

IEEE Embed. Syst. Lett., December, 2024

VALIANT: An EDA Flow for Side-Channel Leakage Evaluation and Tailored Protection.

Rajat Sadhukhan, Sayandeep Saha, Sudipta Paria, Swarup Bhunia, Debdeep Mukhopadhyay

IEEE Trans. Computers, February, 2024

Splitting the Secrets: A Cooperative Trust Model for System-on-Chip Designs with Untrusted IPs.

Aritra Dasgupta, Sudipta Paria, Prabuddha Chakraborty, Swarup Bhunia

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

IP Security in Structured ASIC: Challenges and Prospects.

Rasheed Almawzan, Sudipta Paria, Aritra Dasgupta, Kostas Amberiadis, Swarup Bhunia

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

DiSPEL: A Framework for SoC Security Policy Synthesis and Distributed Enforcement.

Sudipta Paria, Aritra Dasgupta, Swarup Bhunia

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2024

Navigating SoC Security Landscape on LLM-Guided Paths.

Sudipta Paria, Aritra Dasgupta, Swarup Bhunia

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

LATENT: Leveraging Automated Test Pattern Generation for Hardware Trojan Detection.

Sudipta Paria, Pravin Gaikwad, Aritra Dasgupta, Swarup Bhunia

Proceedings of the 33rd IEEE Asian Test Symposium, 2024

2023

DIVAS: An LLM-based End-to-End Framework for SoC Security Analysis and Policy-based Protection.

Sudipta Paria, Aritra Dasgupta, Swarup Bhunia

CoRR, 2023

DiSPEL: Distributed Security Policy Enforcement for Bus-based SoC.

Sudipta Paria, Swarup Bhunia

CoRR, 2023

2014

Structural analysis and regular expressions based noise elimination from web pages for web content mining.

Amit Dutta, Sudipta Paria, Tanmoy Golui, Dipak K. Kole

Proceedings of the 2014 International Conference on Advances in Computing, 2014