Rajat Sadhukhan

Orcid: 0000-0002-2922-9517

According to our database1, Rajat Sadhukhan authored at least 25 papers between 2017 and 2024.

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Bibliography

2024
VALIANT: An EDA Flow for Side-Channel Leakage Evaluation and Tailored Protection.
IEEE Trans. Computers, February, 2024

2023
FHEDA: Efficient Circuit Synthesis with Reduced Bootstrapping for Torus FHE.
IACR Cryptol. ePrint Arch., 2023

Generating Secure Hardware using ChatGPT Resistant to CWEs.
IACR Cryptol. ePrint Arch., 2023

How Hardened is Your Hardware? Guiding ChatGPT to Generate Secure Hardware Resistant to CWEs.
Proceedings of the Cyber Security, Cryptology, and Machine Learning, 2023

Netlist Whisperer: AI and NLP Fight Circuit Leakage!
Proceedings of the 2023 Workshop on Attacks and Solutions in Hardware Security, 2023

2022
A Classical and Machine Learning-Based Reliability Analysis on Catalan Object Encryption Scheme.
IEEE Trans. Reliab., 2022

Light but Tight: Lightweight Composition of Serialized S-Boxes with Diffusion Layers for Strong Ciphers.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2022

AntiSIFA-CAD: A Framework to Thwart SIFA at the Layout Level.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

FUNDAE: Fault Template Attack on SUNDAE-GIFT AEAD Scheme.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2022

2021
Shortest Path to Secured Hardware: Domain Oriented Masking with High-Level-Synthesis.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
Stupify: A Hardware Countermeasure of KRACKs in WPA2 using Physically Unclonable Functions.
Proceedings of the Companion of The 2020 Web Conference 2020, 2020

Design Automation for Side Channel Resistant Lightweight Cryptography.
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

2019
Power Efficiency of S-Boxes: From a Machine-Learning-Based Tool to a Deterministic Model.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Building PUF Based Authentication and Key Exchange Protocol for IoT Without Explicit CRPs in Verifier Database.
IEEE Trans. Dependable Secur. Comput., 2019

Modeling Power Efficiency of S-boxes Using Machine Learning.
IACR Cryptol. ePrint Arch., 2019

Count Your Toggles: a New Leakage Model for Pre-Silicon Power Analysis of Crypto Designs.
J. Electron. Test., 2019

A Machine Learning Based Approach to Predict Power Efficiency of S-Boxes.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

United We Stand: A Threshold Signature Scheme for Identifying Outliers in PLCs.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Lightweight and Side-channel Secure 4 × 4 S-Boxes from Cellular Automata Rules.
IACR Trans. Symmetric Cryptol., 2018

Lightweight and Side-channel Secure 4x4 S-Boxes from Cellular Automata Rules.
IACR Cryptol. ePrint Arch., 2018

PUFSSL: An OpenSSL Extension for PUF based Authentication.
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018

DFARPA: Differential fault attack resistant physical design automation.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
An Evaluation of Lightweight Block Ciphers for Resource-Constrained Applications: Area, Performance, and Security.
J. Hardw. Syst. Secur., 2017

Lightweight Design Choices for LED-like Block Ciphers.
IACR Cryptol. ePrint Arch., 2017

PUF+IBE: Blending Physically Unclonable Functions with Identity Based Encryption for Authentication and Key Exchange in IoTs.
IACR Cryptol. ePrint Arch., 2017


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