Suge Yue

According to our database1, Suge Yue authored at least 10 papers between 2007 and 2016.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2016
A 8.0Gb/s source-series-terminated transmitter driver with 3 tap FFE for multi-standard applications in 65 nm CMOS.
Proceedings of the International Conference on Control, 2016

2011
Impact of Synthesis Constraints on Error Propagation Probability of Digital Circuits.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

Analysis of the New Latchup Model for Deep Sub-micron Integrated Circuits.
Proceedings of the IEEE Ninth International Conference on Dependable, 2011

New Latch-Up Model for Deep Sub-micron Integrated Circuits.
Proceedings of the IEEE Ninth International Conference on Dependable, 2011

2009
3D Simulation of Charge Collection and MNU in Highly-Scaled SRAM Design.
Proceedings of the International Conference on Networked Computing and Advanced Information Management, 2009

2008
FITVS: A FPGA-Based Emulation Tool For High-Efficiency Hardness Evaluation.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2008

A low-voltage CMOS low-dropout regulator with novel capacitor-multiplier frequency compensation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

An Efficient Design of Single Event Transients Tolerance for Logic Circuits.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

2007
An SEU-Tolerant Programmable Frequency Divider.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Capacitor-Multiplier Frequency Compensation for Low-Power Multistage Amplifiers.
Proceedings of the 14th IEEE International Conference on Electronics, 2007


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