William H. Robinson

Orcid: 0000-0001-9291-689X

According to our database1, William H. Robinson authored at least 50 papers between 2001 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
Measuring and Mitigating Bias in AI-Chatbots.
Proceedings of the IEEE International Conference on Assured Autonomy, 2022

Understanding time-varying vulnerability accross GPU Program Lifetime.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022

Model-Based Analysis of Single-Event Upset (SEU) Vulnerability of 6T SRAM Using FinFET Technologies.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022

2021
Evaluating Soft Error Mitigation Trade-offs During Early Design Stages.
Proceedings of the Architecture of Computing Systems - 34th International Conference, 2021

2020
Using Deep Learning to Identify Security Risks of Personal Mobile Devices in Enterprise Networks.
Proceedings of the 11th IEEE Annual Ubiquitous Computing, 2020

A Black Box Approach to Inferring, Characterizing, and Breaking Native Device Tracking Autonomy.
Proceedings of the 11th IEEE Annual Ubiquitous Computing, 2020

Gem5Panalyzer: A Light-weight tool for Early-stage Architectural Reliability Evaluation & Prediction.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

Electrical Masking Improvement with Standard Logic Cell Synthesis Using 45 nm Technology Node.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

Bio-Inspired, Host-based Firewall.
Proceedings of the 23rd IEEE International Conference on Computational Science and Engineering, 2020

Privacy Violating Opensource Intelligence Threat Evaluation Framework: A Security Assessment Framework For Critical Infrastructure Owners.
Proceedings of the 10th Annual Computing and Communication Workshop and Conference, 2020

2019
Error Estimation and Error Reduction With Input-Vector Profiling for Timing Speculation in Digital Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Pulse Broadening in Combinational Circuits with Standard Logic Cell Synthesis.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

2018
Effects of Voltage and Temperature Variations on the Electrical Masking Capability of Sub-65 nm Combinational Logic Circuits.
Proceedings of the 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2018

Network-based detection of mobile malware exhibiting obfuscated or silent network behavior.
Proceedings of the 15th IEEE Annual Consumer Communications & Networking Conference, 2018

2017
On The Outside Looking In: Towards Detecting Counterfeit Devices Using Network Traffic Analysis.
IEEE Trans. Multi Scale Comput. Syst., 2017

A mobile two-way wireless covert timing channel suitable for peer-to-peer malware.
Proceedings of the 28th IEEE Annual International Symposium on Personal, 2017

The effects of radiation-induced soft errors on hardware implementations of object-tracking algorithms.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Using semi-supervised machine learning to address the Big Data problem in DNS networks.
Proceedings of the IEEE 7th Annual Computing and Communication Workshop and Conference, 2017

Using network traffic to verify mobile device forensic artifacts.
Proceedings of the 14th IEEE Annual Consumer Communications & Networking Conference, 2017

2016
Detection of Hardware Trojans in Third-Party Intellectual Property Using Untrusted Modules.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Addressing Negative Racial and Gendered Experiences That Discourage Academic Careers in Engineering.
Comput. Sci. Eng., 2016

Securing commercial WiFi-based UAVs from common security attacks.
Proceedings of the 2016 IEEE Military Communications Conference, 2016

A Dual-Threshold Voltage Approach for Timing Speculation in CMOS Circuits.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

2015
Single-Event Multiple-Transient Characterization and Mitigation via Alternative Standard Cell Placement Methods.
ACM Trans. Design Autom. Electr. Syst., 2015

Using Network Traffic to Infer Hardware State: A Kernel-Level Investigation.
ACM Trans. Embed. Comput. Syst., 2015

A one Zener diode, one memristor crossbar architecture for a write-time-based PUF.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

Using inherent command and control vulnerabilities to halt DDoS attacks.
Proceedings of the 10th International Conference on Malicious and Unwanted Software, 2015

Remotely inferring device manipulation of industrial control systems via network behavior.
Proceedings of the 40th IEEE Local Computer Networks Conference Workshops, 2015

2014
Identification of Trojans in an FPGA using low-precision equipment.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

Fighting banking botnets by exploiting inherent command and control vulnerabilities.
Proceedings of the 9th International Conference on Malicious and Unwanted Software: The Americas MALWARE 2014, 2014

Impact of Process Variations on Reliability and Performance of 32-nm 6T SRAM at Near Threshold Voltage.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Alternative Standard Cell Placement Strategies for Single-Event Multiple-Transient Mitigation.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Constructing timing-based covert channels in mobile networks by adjusting CPU frequency.
Proceedings of the HASP 2014, 2014

2013
Asynchronous Data Sampling Within Clock-Gated Double Edge-Triggered Flip-Flops.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

An efficient technique to select logic nodes for single event transient pulse-width reduction.
Microelectron. Reliab., 2013

Aerial MANETs: Developing a Resilient and Efficient Platform for Search and Rescue Applications.
J. Commun., 2013

Filtergraph: An interactive web application for visualization of astronomy datasets.
Astron. Comput., 2013

Timing analysis in software and hardware to implement NIST elliptic curves over prime fields.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Resilient and efficient MANET aerial communications for search and rescue applications.
Proceedings of the International Conference on Computing, Networking and Communications, 2013

2012
Stealth assessment of hardware Trojans in a microcontroller.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

2011
A Passive Solution to the CPU Resource Discovery Problem in Cluster Grid Networks.
IEEE Trans. Parallel Distributed Syst., 2011

Design Comparison to Identify Malicious Hardware in External Intellectual Property.
Proceedings of the IEEE 10th International Conference on Trust, 2011

Hardware Trojans: The defense and attack of integrated circuits.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Impact of Synthesis Constraints on Error Propagation Probability of Digital Circuits.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

2010
A Passive Solution to the Memory Resource Discovery Problem in Computational Clusters.
IEEE Trans. Netw. Serv. Manag., 2010

A distributed intrusion detection system for resource-constrained devices in ad-hoc networks.
Ad Hoc Networks, 2010

2009
Fault Tolerance in MANETs Using a Task-to-Resource Reallocation Framework.
Proceedings of the 12th IEEE International Conference on Computational Science and Engineering, 2009

2007
Embedded Intelligent Intrusion Detection: A Behavior-Based Approach.
Proceedings of the 21st International Conference on Advanced Information Networking and Applications (AINA 2007), 2007

2005
Efficiency Analysis for a Mixed-Signal Focal Plane Processing Architecture.
J. VLSI Signal Process., 2005

2001
Cost Modeling or Early Image Processing Applications.
Proceedings of the 2nd International Workshop on Digital and Computational Video (DCV 2001), 2001


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