Daniel B. Limbrick
According to our database1,
Daniel B. Limbrick
authored at least 20 papers
between 2011 and 2024.
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Bibliography
2024
FL-IDS: Federated Learning-Based Intrusion Detection System Using Edge Devices for Transportation IoT.
IEEE Access, 2024
2023
A Survey of QEMU-Based Fault Injection Tools & Techniques for Emulating Physical Faults.
IEEE Access, 2023
2022
Evaluating the Impact of Hardware Faults on Program Execution in a Microkernel Environment.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022
Model-Based Analysis of Single-Event Upset (SEU) Vulnerability of 6T SRAM Using FinFET Technologies.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022
2021
Proceedings of the Architecture of Computing Systems - 34th International Conference, 2021
2020
Gem5Panalyzer: A Light-weight tool for Early-stage Architectural Reliability Evaluation & Prediction.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
Electrical Masking Improvement with Standard Logic Cell Synthesis Using 45 nm Technology Node.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
2019
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
2018
Effects of Voltage and Temperature Variations on the Electrical Masking Capability of Sub-65 nm Combinational Logic Circuits.
Proceedings of the 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2018
2017
The effects of radiation-induced soft errors on hardware implementations of object-tracking algorithms.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
2015
Single-Event Multiple-Transient Characterization and Mitigation via Alternative Standard Cell Placement Methods.
ACM Trans. Design Autom. Electr. Syst., 2015
Proceedings of the 24th International Conference on Computer Communication and Networks, 2015
2013
An efficient technique to select logic nodes for single event transient pulse-width reduction.
Microelectron. Reliab., 2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
2011
Proceedings of the IEEE 10th International Conference on Trust, 2011
Impact of Synthesis Constraints on Error Propagation Probability of Digital Circuits.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011