Suhas M. Satheesh

According to our database, Suhas M. Satheesh authored at least 4 papers between 2012 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2022

On-Die Noise Measurement During Automatic Test Equipment (ATE) Testing and In-System-Test (IST).

Seyed Nima Mozaffari, Bonita Bhaskaran, Shantanu Sarangi, Suhas M. Satheesh, Kuo Lin Fu, Nithin Valentine, P. Manikandan, Mahmut Yilmaz

Proceedings of the 40th IEEE VLSI Test Symposium, 2022

2013

Effect of TSV fabrication technology on power distribution in 3D ICs.

Suhas M. Satheesh, Emre Salman

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

2012

Power Distribution in TSV-Based 3-D Processor-Memory Stacks.

Suhas M. Satheesh, Emre Salman

IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

Design space exploration for robust power delivery in TSV based 3-D systems-on-chip.

Suhas M. Satheesh, Emre Salman

Proceedings of the IEEE 25th International SOC Conference, 2012