Shantanu Sarangi

According to our database, Shantanu Sarangi authored at least 12 papers between 2011 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

NVIDIA MATHS: Mechanism to Access Test-Data Over High-Speed Links.

Mahmut Yilmaz, Pavan Kumar Datla Jagannadha, Kaushik Narayanun, Shantanu Sarangi, Francisco Da Silva, Joe Sarmiento

IEEE Des. Test, August, 2023

2022

NVIDIA MATHS: Mechanism to Access Test-Data over High-Speed Links.

Mahmut Yilmaz, Pavan Kumar Datla Jagannadha, Kaushik Narayanun, Shantanu Sarangi, Francisco Da Silva, Joe Sarmiento, Smbat Tonoyan, Ashwin Chintaluri, Animesh Khare, Milind Sonawane, Ashish Kumar, Anitha Kalva, Alex Hsu, Jayesh Pandey

Proceedings of the 40th IEEE VLSI Test Symposium, 2022

On-Die Noise Measurement During Automatic Test Equipment (ATE) Testing and In-System-Test (IST).

Seyed Nima Mozaffari, Bonita Bhaskaran, Shantanu Sarangi, Suhas M. Satheesh, Kuo Lin Fu, Nithin Valentine, P. Manikandan, Mahmut Yilmaz

Proceedings of the 40th IEEE VLSI Test Symposium, 2022

2020

A Novel Graph-Coloring-Based Solution for Low-Power Scan Shift.

Saurabh Gupta, Bonita Bhaskaran, Shantanu Sarangi, Ayub Abdollahian, Jennifer Dworak

IEEE Des. Test, 2020

2019

Hybrid Performance Modeling for Optimization of In-System-Structural-Test (ISST) Latency.

Milind Sonawane, Venkat Abilash Reddy Nerallapally, Alex Hsu, Shantanu Sarangi

Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Special Session: In-System-Test (IST) Architecture for NVIDIA Drive-AGX Platforms.

Pavan Kumar Datla Jagannadha, Mahmut Yilmaz, Milind Sonawane, Sailendra Chadalavada, Shantanu Sarangi, Bonita Bhaskaran, Shashank Bajpai, Venkat Abilash Reddy Nerallapally, Jayesh Pandey, Sam Jiang

Proceedings of the 37th IEEE VLSI Test Symposium, 2019

An Efficient Supervised Learning Method to Predict Power Supply Noise During At-speed Test.

Seyed Nima Mozaffari, Bonita Bhaskaran, Kaushik Narayanun, Ayub Abdollahian, Vinod Pagalone, Shantanu Sarangi, Jonathon E. Colburn

Proceedings of the IEEE International Test Conference, 2019

2017

At-speed capture global noise reduction & low-power memory test architecture.

Bonita Bhaskaran, Sailendra Chadalavada, Shantanu Sarangi, Nithin Valentine, Venkat Abilash Reddy Nerallapally, Ayub Abdollahian

Proceedings of the 35th IEEE VLSI Test Symposium, 2017

2016

Dynamic docking architecture for concurrent testing and peak power reduction.

Milind Sonawane, Pavan Kumar Datla Jagannadha, Sailendra Chadalavada, Shantanu Sarangi, Mahmut Yilmaz, Amit Sanghani, Karthikeyan Natarajan, Jonathon E. Colburn, Anubhav Sinha

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Flexible scan interface architecture for complex SoCs.

Milind Sonawane, Sailendra Chadalavada, Shantanu Sarangi, Amit Sanghani, Mahmut Yilmaz, Pavan Kumar Datla Jagannadha, Jonathon E. Colburn

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Advanced test methodology for complex SoCs.

Pavan Kumar Datla Jagannadha, Mahmut Yilmaz, Milind Sonawane, Sailendra Chadalavada, Shantanu Sarangi, Bonita Bhaskaran, Ayub Abdollahian

Proceedings of the 2016 IEEE International Test Conference, 2016

2011

A clock-gating based capture power droop reduction methodology for at-speed scan testing.

Bo Yang, Amit Sanghani, Shantanu Sarangi, Chunsheng Liu

Proceedings of the Design, Automation and Test in Europe, 2011