Mahmut Yilmaz

According to our database1, Mahmut Yilmaz authored at least 26 papers between 2006 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
Special Session: In-System-Test (IST) Architecture for NVIDIA Drive-AGX Platforms.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

2016
Dynamic docking architecture for concurrent testing and peak power reduction.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Flexible scan interface architecture for complex SoCs.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Advanced test methodology for complex SoCs.
Proceedings of the 2016 IEEE International Test Conference, 2016

2014
Output Deviations-Based SDD Testing.
Proceedings of the Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits., 2014

Circuit Path Grading Considering Layout, Process Variations, and Cross Talk.
Proceedings of the Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits., 2014

2013
Crosstalk- and Process Variations-Aware High-Quality Tests for Small-Delay Defects.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Efficient Pattern Generation for Small-Delay Defects Using Selection of Critical Faults.
J. Electron. Test., 2013

2012
Robust Timing-Aware Test Generation Using Pseudo-Boolean Optimization.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011
A Metric to Target Small-Delay Defects in Industrial Circuits.
IEEE Des. Test Comput., 2011

Critical Fault-Based Pattern Generation for Screening SDDs.
Proceedings of the 16th European Test Symposium, 2011

2010
Test-Pattern Selection for Screening Small-Delay Defects in Very-Deep Submicrometer Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

A novel hybrid method for SDD pattern grading and selection.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

The scan-DFT features of AMD's next-generation microprocessor core.
Proceedings of the 2011 IEEE International Test Conference, 2010

RT-level design-for-testability and expansion of functional test sequences for enhanced defect coverage.
Proceedings of the 2011 IEEE International Test Conference, 2010

High-quality pattern selection for screening small-delay defects considering process variations and crosstalk.
Proceedings of the Design, Automation and Test in Europe, 2010

A Noise-Aware Hybrid Method for SDD Pattern Grading and Selection.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

Circuit Topology-Based Test Pattern Generation for Small-Delay Defects.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009
Automated Test Grading and Pattern Selection for Small-Delay Defects.
PhD thesis, 2009

Seed selection in LFSR-reseeding-based test compression for the detection of small-delay defects.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Test-Pattern Grading and Pattern Selection for Small-Delay Defects.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Interconnect-Aware and Layout-Oriented Test-Pattern Selection for Small-Delay Defects.
Proceedings of the 2008 IEEE International Test Conference, 2008

2007
Low-cost run-time diagnosis of hard delay faults in the functional units of a microprocessor.
Proceedings of the 25th International Conference on Computer Design, 2007

Lazy Error Detection for Microprocessor Functional Units.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

2006
Applying architectural vulnerability Analysis to hard faults in the microprocessor.
Proceedings of the Joint International Conference on Measurement and Modeling of Computer Systems, 2006

Self-Checking and Self-Diagnosing 32-bit Microprocessor Multiplier.
Proceedings of the 2006 IEEE International Test Conference, 2006


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