Andres Goens

According to our database1, Andres Goens authored at least 18 papers between 2014 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 





Category-Theoretic Foundations of "STCLang: State Thread Composition as a Foundation for Monadic Dataflow Parallelism".
CoRR, 2019

On Compact Mappings for Multicore Systems.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

STCLang: state thread composition as a foundation for monadic dataflow parallelism.
Proceedings of the 12th ACM SIGPLAN International Symposium on Haskell, 2019

Actors Revisited for Time-Critical Systems.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

A Hardware/Software Stack for Heterogeneous Systems.
IEEE Trans. Multi-Scale Computing Systems, 2018

On the Representation of Mappings to Multicores.
Proceedings of the 12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2018

Implicit Data-Parallelism in Kahn Process Networks: Bridging the MacQueen Gap.
Proceedings of the 9th Workshop on Parallel Programming and RunTime Management Techniques for Manycore Architectures and 7th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2018

Compiling for concise code and efficient I/O.
Proceedings of the 27th International Conference on Compiler Construction, 2018

Symmetry in Software Synthesis.
TACO, 2017

Symmetry in Software Synthesis.
CoRR, 2017

Robust Mapping of Process Networks to Many-Core Systems using Bio-Inspired Design Centering.
Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems, 2017

TETRiS: a Multi-Application Run-Time System for Predictable Execution of Static Mappings.
Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems, 2017

An optimal allocation of memory buffers for complex multicore platforms.
Journal of Systems Architecture - Embedded Systems Design, 2016

High-level NoC model for MPSoC compilers.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016

Why Comparing System-Level MPSoC Mapping Approaches is Difficult: A Case Study.
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016

Buffer Allocation Based On-Chip Memory Optimization for Many-Core Platforms.
Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 2015

Analysis of Process Traces for Mapping Dynamic KPN Applications to MPSoCs.
Proceedings of the System Level Design from HW/SW to Memory for Embedded Systems, 2015

Optimized buffer allocation in multicore platforms.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014