Serif Yesil

Orcid: 0000-0002-7947-2451

According to our database1, Serif Yesil authored at least 18 papers between 2015 and 2023.

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Bibliography

2023
Efficient parallel implementation of the multiplicative weight update method for graph-based linear programs.
CoRR, 2023

Input-sensitive dense-sparse primitive compositions for GNN acceleration.
CoRR, 2023

WISE: Predicting the Performance of Sparse Matrix Vector Multiplication with Machine Learning.
Proceedings of the 28th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming, 2023

SPADE: A Flexible and Scalable Accelerator for SpMM and SDDMM.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

2022
Scheduling for heterogeneous systems in accelerator-rich environments.
J. Supercomput., 2022

Dense dynamic blocks: optimizing SpMM for processors with vector and matrix units using machine learning techniques.
Proceedings of the ICS '22: 2022 International Conference on Supercomputing, Virtual Event, June 28, 2022

2020
Speeding up SpMV for power-law graph analytics by enhancing locality & vectorization.
Proceedings of the International Conference for High Performance Computing, 2020

V-Combiner: speeding-up iterative graph processing on a shared-memory platform with vertex merging.
Proceedings of the ICS '20: 2020 International Conference on Supercomputing, 2020

Snug: architectural support for relaxed concurrent priority queueing in chip multiprocessors.
Proceedings of the ICS '20: 2020 International Conference on Supercomputing, 2020

2019
Understanding priority-based scheduling of graph algorithms on a shared-memory platform.
Proceedings of the International Conference for High Performance Computing, 2019

2018
A Template-Based Design Methodology for Graph-Parallel Hardware Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Toward Dynamic Precision Scaling.
IEEE Micro, 2018

2017
Graph Analytics Accelerators for Cognitive Systems.
IEEE Micro, 2017

On Dynamic Precision Scaling.
CoRR, 2017

2016
Energy Efficient Architecture for Graph Analytics Accelerators.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

FPGA implementation of a fault-tolerant application-specific NoC design.
Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016

2015
Hardware Accelerator Design for Data Centers.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Architectural Requirements for Energy Efficient Execution of Graph Analytics Applications.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015


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