Suman Sau

According to our database, Suman Sau authored at least 17 papers between 2011 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2021

Voltage Scaling for Partitioned Systolic Array in A Reconfigurable Platform.

Rourab Paul, Sreetama Sarkar, Suman Sau, Koushik Chakraborty, Sanghamitra Roy, Amlan Chakrabarti

CoRR, 2021

Blockchain based secure smart city architecture using low resource IoTs.

Rourab Paul, Nimisha Ghosh, Suman Sau, Amlan Chakrabarti, Prasant Mohapatra

Comput. Networks, 2021

2019

IoT based Smart Access Controlled Secure Smart City Architecture Using Blockchain.

Rourab Paul, Nimisha Ghosh, Suman Sau, Amlan Chakrabarti, Prasant Mahapatra

CoRR, 2019

2018

A New High Throughput and Area Efficient SHA-3 Implementation.

Ming Ming Wong, Jawad Haj-Yahya, Suman Sau, Anupam Chattopadhyay

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

Efficient dynamic priority based soft error mitigation techniques for configuration memory of FPGA hardware.

Swagata Mandal, Rourab Paul, Suman Sau, Amlan Chakrabarti, Subhasis Chattopadhyay

Microprocess. Microsystems, 2017

Survey of secure processors.

Suman Sau, Jawad Haj-Yahya, Ming Ming Wong, Kwok-Yan Lam, Anupam Chattopadhyay

Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

2016

A Novel Method for Soft Error Mitigation in FPGA Using Modified Matrix Code.

Swagata Mandal, Rourab Paul, Suman Sau, Amlan Chakrabarti, Subhasis Chattopadhyay

IEEE Embed. Syst. Lett., 2016

2015

High speed fault tolerant secure communication for muon chamber using fpga based gbt emulator.

Suman Sau, Swagata Mandal, Jogender Saini, Amlan Chakrabarti, Subhasis Chattopadhyay

CoRR, 2015

FPGA based High Speed Data Acquisition System for High Energy Physics Application.

Swagata Mandal, Suman Sau, Amlan Chakrabarti, Subhasis Chattopadhyay

CoRR, 2015

A Novel Method for Soft Error Mitigation in FPGA using Adaptive Cross Parity Code.

Swagata Mandal, Rourab Paul, Suman Sau, Amlan Chakrabarti, Subhasis Chattopadhyay

CoRR, 2015

FPGA Based Novel High Speed DAQ System Design with Error Correction.

Swagata Mandal, Suman Sau, Amlan Chakrabarti, Jogendra Saini, Sushanta Kumar Pal, Subhasish Chattopadhyay

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

FPGA Implementation of High Speed Latency Optimized Optical Communication System Based on Orthogonal Concatenated Code.

Swagata Mandal, Suman Sau, Amlan Chakrabarti, Sushanta Kumar Pal, Subhasish Chattopadhyay

Proceedings of the 24th IEEE Asian Test Symposium, 2015

2012

A brief experience on journey through hardware developments for image processing and its applications on Cryptography

Sangeet Saha, Chandrajit Pal, Rourab Paul, Satyabrata Maity, Suman Sau

CoRR, 2012

Architecture for real time continuous sorting on large width data volume for fpga based applications

Rourab Paul, Suman Sau, Amlan Chakrabarti

CoRR, 2012

Design and implementation of real time AES-128 on real time operating system for multiple FPGA communication

Rourab Paul, Sangeet Saha, Suman Sau, Amlan Chakrabarti

CoRR, 2012

A novel AES-256 implementation on FPGA using co-processor based architecture.

Suman Sau, Rourab Paul, Tanmay Biswas, Amlan Chakrabarti

Proceedings of the 2012 International Conference on Advances in Computing, 2012

2011

Design and implementation of real time secured RS232 link for multiple FPGA communication.

Suman Sau, Chandrajit Pal, Amlan Chakrabarti

Proceedings of the 2011 International Conference on Communication, 2011