Sreetama Sarkar

Orcid: 0009-0009-2182-6200

According to our database1, Sreetama Sarkar authored at least 7 papers between 2018 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Linearizing Models for Efficient yet Robust Private Inference.
CoRR, 2024

2023
Technology-Circuit-Algorithm Tri-Design for Processing-in-Pixel-in-Memory (P2M).
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

2022
Accelerating and pruning CNNs for semantic segmentation on FPGA.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
Voltage Scaling for Partitioned Systolic Array in A Reconfigurable Platform.
CoRR, 2021

Adversarial Robust Model Compression Using In-Train Pruning.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition Workshops, 2021

2019
Criticality Aware Soft Error Mitigation in the Configuration Memory of SRAM Based FPGA.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

2018
Implementation of relay hopper model for reliable communication of IoT devices in LTE environment through D2D link.
Proceedings of the 10th International Conference on Communication Systems & Networks, 2018


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