Suresh Purini

Orcid: 0000-0001-5094-995X

According to our database1, Suresh Purini authored at least 35 papers between 2007 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
FlowPix: Accelerating Image Processing Pipelines on an FPGA Overlay using a Domain Specific Compiler.
ACM Trans. Archit. Code Optim., December, 2023

Hardware Accelerator for Transformer based End-to-End Automatic Speech Recognition System.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2023

Building Low-Latency Order Books with Hybrid Binary-Linear Search Data Structures on FPGAs.
Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

A Cloud-Fog Architecture for Video Analytics on Large Scale Camera Networks Using Semantic Scene Analysis.
Proceedings of the 23rd IEEE/ACM International Symposium on Cluster, 2023

2022
An FPGA Overlay for CNN Inference with Fine-grained Flexible Parallelism.
ACM Trans. Archit. Code Optim., 2022

Accuracy Configurable FPGA Implementation of Harris Corner Detection.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

Systolic Array based FPGA accelerator for Yolov3-tiny.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2022

2021
Pricing strategies of an oligopolist in federated cloud markets.
J. Cloud Comput., 2021

2020
Model Checking as a Service using Dynamic Resource Scaling.
Proceedings of the 27th IEEE International Conference on High Performance Computing, 2020

FPGA Accelerator for Stereo Vision using Semi-Global Matching through Dependency Relaxation.
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

Accelerating Local Laplacian Filters on FPGAs.
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

Bitwidth customization in image processing pipelines using interval analysis and SMT solvers.
Proceedings of the CC '20: 29th International Conference on Compiler Construction, 2020

2018
Synthesizing Power and Area Efficient Image Processing Pipelines on FPGAs using Customized Bit-widths.
CoRR, 2018

A Multi-Cloud Marketplace Model with Multiple Brokers for IaaS Layer and Generalized Stable Matching.
Proceedings of the 11th IEEE/ACM International Conference on Utility and Cloud Computing, 2018

Flow Sensor IoT Node for Wi-Fi Equipped Apartments and Gated Communities.
Proceedings of the 2018 IEEE SENSORS, New Delhi, India, October 28-31, 2018, 2018

Share-a-GPU: Providing Simple and Effective Time-Sharing on GPUs.
Proceedings of the 25th IEEE International Conference on High Performance Computing, 2018

Cloud Federation Formation in Oligopolistic Markets.
Proceedings of the Euro-Par 2018: Parallel Processing, 2018

2017
Unsupervised Learning Based Approach for Plagiarism Detection in Programming Assignments.
Proceedings of the 10th Innovations in Software Engineering Conference, 2017

Plagiarism Detection in Programming Assignments Using Deep Features.
Proceedings of the 4th IAPR Asian Conference on Pattern Recognition, 2017

2016
Fast algorithms for optimal coalition formation in federated clouds.
Proceedings of the 9th International Conference on Utility and Cloud Computing, 2016

Accurus: A Fast Convergence Technique for Accuracy Configurable Approximate Adder Circuits.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Distributed Safety Verification Using Vertex Centric Programming Model.
Proceedings of the 15th International Symposium on Parallel and Distributed Computing, 2016

A Hybrid CPU+GPU Working-Set Dictionary.
Proceedings of the 15th International Symposium on Parallel and Distributed Computing, 2016

Anuvaad Pranaali: A RESTful API for Machine Translation.
Proceedings of the Service-Oriented Computing - ICSOC 2016 Workshops, 2016

Re-targeting Optimization Sequences from Scalar Processors to FPGAs in HLS compilers (Abstract Only).
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

A DSL Compiler for Accelerating Image Processing Pipelines on FPGAs.
Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, 2016

2015
Dynamic Memory and Core Scaling in Virtual Machines.
Proceedings of the 8th IEEE International Conference on Cloud Computing, 2015

2014
RLC - A Reliable Approach to Fast and Efficient Live Migration of Virtual Machines in the Clouds.
Proceedings of the 2014 IEEE 7th International Conference on Cloud Computing, Anchorage, AK, USA, June 27, 2014

2013
Finding good optimization sequences covering program space.
ACM Trans. Archit. Code Optim., 2013

Virtual Machine Coscheduling: A Game Theoretic Approach.
Proceedings of the IEEE/ACM 6th International Conference on Utility and Cloud Computing, 2013

2010
Design of Low Power Systems Using Inexact Logic Circuits.
J. Low Power Electron., 2010

Transition Inversion Based Low Power Data Coding Scheme for Buffered Data Transfer.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

Inexact Decision Circuits: An Application to Hamming Weight Threshold Voting.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

2008
Amplifying ZPP^SAT[1] and the Two Queries Problem.
Proceedings of the 23rd Annual IEEE Conference on Computational Complexity, 2008

2007
Bounded Queries and the NP Machine Hypothesis.
Proceedings of the 22nd Annual IEEE Conference on Computational Complexity (CCC 2007), 2007


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