Uday Bondhugula

According to our database, Uday Bondhugula authored at least 54 papers between 2005 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Automatic multi-dimensional pipelining for high-level synthesis of dataflow accelerators.

Kingshuk Majumder, Uday Bondhugula

CoRR, 2023

HIR: An MLIR-based Intermediate Representation for Hardware Accelerator Description.

Kingshuk Majumder, Uday Bondhugula

Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

2022

Treebeard: An Optimizing Compiler for Decision Tree Based ML Inference.

Ashwin Prasad, Sampath Rajendra, Kaushik Rajan, R. Govindarajan, Uday Bondhugula

Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

MLIR-based code generation for GPU tensor cores.

Navdeep Katel, Vivek Khandelwal, Uday Bondhugula

Proceedings of the CC '22: 31st ACM SIGPLAN International Conference on Compiler Construction, Seoul, South Korea, April 2, 2022

2021

High Performance GPU Code Generation for Matrix-Matrix Multiplication using MLIR: Some Early Results.

Navdeep Katel, Vivek Khandelwal, Uday Bondhugula

CoRR, 2021

A practical tile size selection model for affine loop nests.

Kumudha Narasimhan, Aravind Acharya, Abhinav Baid, Uday Bondhugula

Proceedings of the ICS '21: 2021 International Conference on Supercomputing, 2021

MLIR: Scaling Compiler Infrastructure for Domain Specific Computation.

Chris Lattner, Mehdi Amini, Uday Bondhugula, Albert Cohen, Andy Davis, Jacques A. Pienaar, River Riddle, Tatiana Shpeisman, Nicolas Vasilache, Oleksandr Zinenko

Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization, 2021

2020

An Effective Fusion and Tile Size Model for PolyMage.

Abhinav Jangda, Uday Bondhugula

ACM Trans. Program. Lang. Syst., 2020

Optimizing the Linear Fascicle Evaluation Algorithm for Multi-core and Many-core Systems.

Karan Aggarwal, Uday Bondhugula

ACM Trans. Parallel Comput., 2020

Effective Loop Fusion in Polyhedral Compilation Using Fusion Conflict Graphs.

Aravind Acharya, Uday Bondhugula, Albert Cohen

ACM Trans. Archit. Code Optim., 2020

High Performance Code Generation in MLIR: An Early Case Study with GEMM.

Uday Bondhugula

CoRR, 2020

MLIR: A Compiler Infrastructure for the End of Moore's Law.

Chris Lattner, Jacques A. Pienaar, Mehdi Amini, Uday Bondhugula, River Riddle, Albert Cohen, Tatiana Shpeisman, Andy Davis, Nicolas Vasilache, Oleksandr Zinenko

CoRR, 2020

Bitwidth customization in image processing pipelines using interval analysis and SMT solvers.

Suresh Purini, Vinamra Benara, Ziaul Choudhury, Uday Bondhugula

Proceedings of the CC '20: 29th International Conference on Compiler Construction, 2020

2019

A flexible FPGA accelerator for convolutional neural networks.

Kingshuk Majumder, Uday Bondhugula

CoRR, 2019

Optimizing the Linear Fascicle Evaluation Algorithm for Multi-Core and Many-Core Systems.

Karan Aggarwal, Uday Bondhugula, Varsha Sreenivasan, Devarajan Sridharan

CoRR, 2019

Optimizing the linear fascicle evaluation algorithm for many-core systems.

Karan Aggarwal, Uday Bondhugula

Proceedings of the ACM International Conference on Supercomputing, 2019

2018

An Approach for Finding Permutations Quickly: Fusion and Dimension matching.

Aravind Acharya, Uday Bondhugula, Albert Cohen

CoRR, 2018

Synthesizing Power and Area Efficient Image Processing Pipelines on FPGAs using Customized Bit-widths.

Vinamra Benara, Sahithi Rampalli, Ziaul Choudhury, Suresh Purini, Uday Bondhugula

CoRR, 2018

An effective fusion and tile size model for optimizing image processing pipelines.

Abhinav Jangda, Uday Bondhugula

Proceedings of the 23rd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2018

Polyhedral auto-transformation with no integer linear programming.

Aravind Acharya, Uday Bondhugula, Albert Cohen

Proceedings of the 39th ACM SIGPLAN Conference on Programming Language Design and Implementation, 2018

2017

Diamond Tiling: Tiling Techniques to Maximize Parallelism for Stencil Computations.

Uday Bondhugula, Vinayaka Bandishti, Irshad Pananilath

IEEE Trans. Parallel Distributed Syst., 2017

Optimizing geometric multigrid method computation using a DSL approach.

Vinay Vasista, Kumudha Narasimhan, Siddharth Bhat, Uday Bondhugula

Proceedings of the International Conference for High Performance Computing, 2017

2016

The Pluto+ Algorithm: A Practical Approach for Parallelization and Locality Optimization of Affine Loop Nests.

Uday Bondhugula, Aravind Acharya, Albert Cohen

ACM Trans. Program. Lang. Syst., 2016

Automatic Storage Optimization for Arrays.

Somashekaracharya G. Bhaskaracharya, Uday Bondhugula, Albert Cohen

ACM Trans. Program. Lang. Syst., 2016

Compiling Affine Loop Nests for a Dynamic Scheduling Runtime on Shared and Distributed Memory.

Roshan Dathathri, Ravi Teja Mullapudi, Uday Bondhugula

ACM Trans. Parallel Comput., 2016

SMO: an integrated approach to intra-array and inter-array storage optimization.

Somashekaracharya G. Bhaskaracharya, Uday Bondhugula, Albert Cohen

Proceedings of the 43rd Annual ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, 2016

A DSL Compiler for Accelerating Image Processing Pipelines on FPGAs.

Nitin Chugh, Vinay Vasista, Suresh Purini, Uday Bondhugula

Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, 2016

2015

An Optimizing Code Generator for a Class of Lattice-Boltzmann Computations.

Irshad Pananilath, Aravind Acharya, Vinay Vasista, Uday Bondhugula

ACM Trans. Archit. Code Optim., 2015

PLUTO+: near-complete modeling of affine transformations for parallelism and locality.

Aravind Acharya, Uday Bondhugula

Proceedings of the 20th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2015

PolyMage: Automatic Optimization for Image Processing Pipelines.

Ravi Teja Mullapudi, Vinay Vasista, Uday Bondhugula

Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems, 2015

2014

Effective automatic computation placement and dataallocation for parallelization of regular programs.

Chandan Reddy, Uday Bondhugula

Proceedings of the 2014 International Conference on Supercomputing, 2014

Tiling and optimizing time-iterated computations on periodic domains.

Uday Bondhugula, Vinayaka Bandishti, Albert Cohen, Guillain Potron, Nicolas Vasilache

Proceedings of the International Conference on Parallel Architectures and Compilation, 2014

2013

Automatic data allocation and buffer management for multi-GPU machines.

Thejas Ramashekar, Uday Bondhugula

ACM Trans. Archit. Code Optim., 2013

Compiling affine loop nests for distributed-memory parallel architectures.

Uday Bondhugula

Proceedings of the International Conference for High Performance Computing, 2013

PolyGLoT: A Polyhedral Loop Transformation Framework for a Graphical Dataflow Language.

Somashekaracharya G. Bhaskaracharya, Uday Bondhugula

Proceedings of the Compiler Construction - 22nd International Conference, 2013

Generating efficient data movement code for heterogeneous architectures with distributed-memory.

Roshan Dathathri, Chandan Reddy, Thejas Ramashekar, Uday Bondhugula

Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013

2012

Tiling stencil computations to maximize parallelism.

Vinayaka Bandishti, Irshad Pananilath, Uday Bondhugula

Proceedings of the SC Conference on High Performance Computing Networking, 2012

2011

Loop transformations: convexity, pruning and optimization.

Louis-Noël Pouchet, Uday Bondhugula, Cédric Bastoul, Albert Cohen, J. Ramanujam, P. Sadayappan, Nicolas Vasilache

Proceedings of the 38th ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, 2011

2010

Combined Iterative and Model-driven Optimization in an Automatic Parallelization Framework.

Louis-Noël Pouchet, Uday Bondhugula, Cédric Bastoul, Albert Cohen, J. Ramanujam, P. Sadayappan

Proceedings of the Conference on High Performance Computing Networking, 2010

Believe it or not!: mult-core CPUs can match GPU performance for a FLOP-intensive application!

Rajesh Bordawekar, Uday Bondhugula, Ravi Rao

Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

A model for fusion and code motion in an automatic parallelizing compiler.

Uday Bondhugula, Oktay Günlük, Sanjeeb Dash, Lakshminarayanan Renganarayanan

Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

2009

Compact multi-dimensional kernel extraction for register tiling.

Lakshminarayanan Renganarayanan, Uday Bondhugula, Salem Derisavi, Alexandre E. Eichenberger, Kevin O'Brien

Proceedings of the ACM/IEEE Conference on High Performance Computing, 2009

Compiler-assisted dynamic scheduling for effective parallelization of loop nests on multicore processors.

Muthu Manikandan Baskaran, Nagavijayalakshmi Vydyanathan, Uday Bondhugula, J. Ramanujam, Atanas Rountev, P. Sadayappan

Proceedings of the 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2009

Data Layout Transformation for Enhancing Data Locality on NUCA Chip Multiprocessors.

Qingda Lu, Christophe Alias, Uday Bondhugula, Thomas Henretty, Sriram Krishnamoorthy, J. Ramanujam, Atanas Rountev, P. Sadayappan, Yongjian Chen, Haibo Lin, Tin-Fook Ngai

Proceedings of the PACT 2009, 2009

2008

Automatic data movement and computation mapping for multi-level parallel architectures with explicitly managed memories.

Muthu Manikandan Baskaran, Uday Bondhugula, Sriram Krishnamoorthy, J. Ramanujam, Atanas Rountev, P. Sadayappan

Proceedings of the 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2008

A practical automatic polyhedral parallelizer and locality optimizer.

Uday Bondhugula, Albert Hartono, J. Ramanujam, P. Sadayappan

Proceedings of the ACM SIGPLAN 2008 Conference on Programming Language Design and Implementation, 2008

Towards effective automatic parallelization for multicore systems.

Uday Bondhugula, Muthu Manikandan Baskaran, Albert Hartono, Sriram Krishnamoorthy, J. Ramanujam, Atanas Rountev, P. Sadayappan

Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

A compiler framework for optimization of affine loop nests for gpgpus.

Muthu Manikandan Baskaran, Uday Bondhugula, Sriram Krishnamoorthy, J. Ramanujam, Atanas Rountev, P. Sadayappan

Proceedings of the 22nd Annual International Conference on Supercomputing, 2008

Automatic Transformations for Communication-Minimized Parallelization and Locality Optimization in the Polyhedral Model.

Uday Bondhugula, Muthu Manikandan Baskaran, Sriram Krishnamoorthy, J. Ramanujam, Atanas Rountev, P. Sadayappan

Proceedings of the Compiler Construction, 17th International Conference, 2008

2007

Automatic mapping of nested loops to FPGAS.

Uday Bondhugula, J. Ramanujam, P. Sadayappan

Proceedings of the 12th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2007

Effective automatic parallelization of stencil computations.

Sriram Krishnamoorthy, Muthu Manikandan Baskaran, Uday Bondhugula, J. Ramanujam, Atanas Rountev, P. Sadayappan

Proceedings of the ACM SIGPLAN 2007 Conference on Programming Language Design and Implementation, 2007

2006

Parallel FPGA-based all-pairs shortest-paths in a directed graph.

Uday Bondhugula, Ananth Devulapalli, Joseph Fernando, Pete Wyckoff, P. Sadayappan

Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Hardware/Software Integration for FPGA-based All-Pairs Shortest-Paths.

Uday Bondhugula, Ananth Devulapalli, James Dinan, Joseph Fernando, Pete Wyckoff, Eric Stahlberg, P. Sadayappan

Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

2005

High Performance RDMA Based All-to-All Broadcast for InfiniBand Clusters.

Sayantan Sur, Uday Bondhugula, Amith R. Mamidala, Hyun-Wook Jin, Dhabaleswar K. Panda

Proceedings of the High Performance Computing, 2005