Shashwat Shrivastava

Orcid: 0000-0003-3816-0061

According to our database1, Shashwat Shrivastava authored at least 6 papers between 2020 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2023
Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs.
J. Hardw. Syst. Secur., September, 2023

IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Mitigating the Last-Mile Bottleneck: A Two-Step Approach For Faster Commercial FPGA Routing.
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

2022
An FPGA Overlay for CNN Inference with Fine-grained Flexible Parallelism.
ACM Trans. Archit. Code Optim., 2022

2020
FPGA Accelerator for Stereo Vision using Semi-Global Matching through Dependency Relaxation.
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

Accelerating Local Laplacian Filters on FPGAs.
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020


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