Sylvain Huet

According to our database1, Sylvain Huet authored at least 23 papers between 2005 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Online Class Incremental Learning with One-Vs-All Classifiers for Resource Constrained Devices.
Proceedings of the International Symposium on Image and Signal Processing and Analysis, 2023

Comparative Study of Natural Replay and Experience Replay in Online Object Detection.
Proceedings of the IEEE/CVF International Conference on Computer Vision, 2023

Moving Towards and Reaching a 3-D Target by Embodied Guidance: Parsimonious Vs Explicit Sound Metaphors.
Proceedings of the Universal Access in Human-Computer Interaction, 2023

2020
Efficient adaptive load balancing approach for compressive background subtraction algorithm on heterogeneous CPU-GPU platforms.
J. Real Time Image Process., 2020

2018
Prototyping and Evaluating Sensory Substitution Devices by Spatial Immersion in Virtual Environments.
Proceedings of the 13th International Joint Conference on Computer Vision, Imaging and Computer Graphics Theory and Applications (VISIGRAPP 2018), 2018

Single Core SIMD Parallelization of GMM Background Subtraction Algorithm for Vehicles Detection.
Proceedings of the 5th IEEE International Congress on Information Science and Technology, 2018

Efficient parallelization of GMM background subtraction algorithm on a multi-core platform for moving objects detection.
Proceedings of the 4th International Conference on Advanced Technologies for Signal and Image Processing, 2018

2016
A domain-specific high-level programming model.
Concurr. Comput. Pract. Exp., 2016

2014
Efficient implementation of data flow graphs on multi-gpu clusters.
J. Real Time Image Process., 2014

SignalPU: A Programming Model for DSP Applications on Parallel and Heterogeneous Clusters.
Proceedings of the 2014 IEEE International Conference on High Performance Computing and Communications, 2014

A Visual Programming Model to Implement Coarse-Grained DSP Applications on Parallel and Heterogeneous Clusters.
Proceedings of the Euro-Par 2014: Parallel Processing Workshops, 2014

2013
Task migration of DSP application specified with a DFG and implemented with the BSP computing model on a CPU-GPU cluster.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

2011
DFG implementation on multi GPU cluster with computation-communication overlap.
Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011

2010
SysCellC: a data-flow programming model on multi-GPU.
Proceedings of the International Conference on Computational Science, 2010

A Programming Model and a NoC-Based Architecture for Streaming Applications.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2008
Dynamic Memory Access Management for High-Performance DSP Applications Using High-Level Synthesis.
IEEE Trans. Very Large Scale Integr. Syst., 2008

SysCellC: SystemC on Cell.
Proceedings of the Selected Papers of the Sixth International Conference on Computational Sciences and Its Applications, 2008

2007
Granularity Issues in Transaction Level Modelling Digital Signal Processing Applications.
Proceedings of the Forum on specification and Design Languages, 2007

2006
Hardware Communication Refinement in Digital Signal Processing.
Proceedings of the Forum on specification and Design Languages, 2006

A Computation Core for Communication Refinement of Digital Signal Processing Algorithms.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

2005
Design Exploration and HW/SW Rapid Prototyping for Real-Time System Design.
Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005

Pipelined Memory Controllers for DSP Applications Handling Unpredictable Data Accesses.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

C-based rapid prototyping for digital signal processing.
Proceedings of the 13th European Signal Processing Conference, 2005


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