Emmanuel Casseau
Orcid: 0000-0001-7216-749X
According to our database1,
Emmanuel Casseau
authored at least 82 papers
between 1994 and 2024.
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Bibliography
2024
Algorithms with improved delay for enumerating connected induced subgraphs of a large cardinality.
Inf. Process. Lett., January, 2024
2023
Sustain. Comput. Informatics Syst., April, 2023
Near-optimal energy-efficient partial-duplication task mapping of real-time parallel applications.
J. Syst. Archit., 2023
Surround the Nonlinearity: Inserting Foldable Convolutional Autoencoders to Reduce Activation Footprint.
Proceedings of the IEEE/CVF International Conference on Computer Vision, 2023
2022
Int. J. Parallel Program., 2022
Proceedings of the International Conference on Management of Data, 2022
2021
Improving the CubeSat reliability thanks to a multiprocessor system using fault tolerant online scheduling.
Microprocess. Microsystems, September, 2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
An algorithm with improved delay for enumerating connected induced subgraphs of a large cardinality.
CoRR, 2021
Special Session: Operating Systems under test: an overview of the significance of the operating system in the resiliency of the computing continuum.
Proceedings of the 39th IEEE VLSI Test Symposium, 2021
Proceedings of the SSDBM 2021: 33rd International Conference on Scientific and Statistical Database Management, 2021
Fault-Tolerant Mapping of Real-Time Parallel Applications under multiple DVFS schemes.
Proceedings of the 27th IEEE Real-Time and Embedded Technology and Applications Symposium, 2021
2020
MASCARA (ModulAr Semantic CAching fRAmework) towards FPGA Acceleration for IoT Security Monitoring.
Open J. Internet Things, 2020
Energy-Aware Partial-Duplication Task Mapping Under Real-Time and Reliability Constraints.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2020
Proceedings of the 11th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures / 9th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2020
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020
2019
Proceedings of the 2019 Conference on Design and Architectures for Signal and Image Processing, 2019
2018
Restricted Scheduling Windows for Dynamic Fault-Tolerant Primary/Backup Approach-Based Scheduling on Embedded Systems.
Proceedings of the 21st International Workshop on Software and Compilers for Embedded Systems, 2018
Comparison of Different Methods Making Use of Backup Copies for Fault-Tolerant Scheduling on Embedded Multiprocessor Systems.
Proceedings of the 2018 Conference on Design and Architectures for Signal and Image Processing, 2018
2017
J. Syst. Archit., 2017
An efficient framework for design and assessment of arithmetic operators with Reduced-Precision Redundancy.
Proceedings of the 2017 Conference on Design and Architectures for Signal and Image Processing, 2017
2016
Microprocess. Microsystems, 2016
Demo abstract: FPGA-based implementation of a flexible FFT dedicated to LTE standard.
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016
On the FPGA-Based Implementation of a Flexible Waveform from a High-Level Description: Application to LTE FFT Case Study.
Proceedings of the Cognitive Radio Oriented Wireless Networks, 2016
2015
J. Signal Process. Syst., 2015
Small FPGA Based Multiplication-Inversion Unit for Normal Basis Representation in GF(2m).
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Proceedings of the 2015 Conference on Design and Architectures for Signal and Image Processing, 2015
Compa backend: A dynamic runtime for the execution of dataflow programs onto multi-core platforms.
Proceedings of the 2015 Conference on Design and Architectures for Signal and Image Processing, 2015
2014
Automatic custom instruction identification for application-specific instruction set processors.
Microprocess. Microsystems, 2014
Place Reservation technique for online task placement on a multi-context heterogeneous reconfigurable architecture.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the IEEE International Conference on Acoustics, 2014
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014
2013
Automated design of networks of transport-triggered architecture processors using dynamic dataflow programs.
Signal Process. Image Commun., 2013
Towards run-time actor mapping of dynamic dataflow programs onto multi-core platforms.
Proceedings of the 8th International Symposium on Image and Signal Processing and Analysis, 2013
2012
Integr., 2012
Scheduling, Binding and Routing System for a Run-Time Reconfigurable Operator Based Multimedia Architecture.
Int. J. Embed. Real Time Commun. Syst., 2012
2011
J. Signal Process. Syst., 2011
EURASIP J. Adv. Signal Process., 2011
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011
Proceedings of the IEEE International Conference on Acoustics, 2011
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011
Proceedings of the 22nd IEEE International Conference on Application-specific Systems, 2011
2010
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
Scheduling, binding and routing system for a run-time reconfigurable operator based multimedia architecture.
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010
2009
Proceedings of the 2009 International Conference on Embedded Computer Systems: Architectures, 2009
Proceedings of the 17th European Signal Processing Conference, 2009
Proceedings of the 20th IEEE International Conference on Application-Specific Systems, 2009
Proceedings of the Reconfigurable Computing: Architectures, 2009
2008
Dynamic Memory Access Management for High-Performance DSP Applications Using High-Level Synthesis.
IEEE Trans. Very Large Scale Integr. Syst., 2008
Synthèse de haut niveau tenant compte de la dynamique des traitements. Analyse de la largeur des données d'applications du TDSI et gestion de cette information lors de la synthèse de haut niveau.
Tech. Sci. Informatiques, 2008
2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Granularity Issues in Transaction Level Modelling Digital Signal Processing Applications.
Proceedings of the Forum on specification and Design Languages, 2007
Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007
2006
A formal method for hardware IP design and integration under I/O and timing constraints.
ACM Trans. Embed. Comput. Syst., 2006
Design of a flexible 2-D discrete wavelet transform IP core for JPEG2000 image coding in embedded imaging systems.
Signal Process., 2006
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006
Bit-Width Optimizations for High-Level Synthesis of Digital Signal Processing Systems.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006
Proceedings of the 13th IEEE International Conference on Electronics, 2006
Proceedings of the Forum on specification and Design Languages, 2006
A Computation Core for Communication Refinement of Digital Signal Processing Algorithms.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006
2005
Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005
Pipelined Memory Controllers for DSP Applications Handling Unpredictable Data Accesses.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005
Pipelined memory controllers for DSP real-time applications handling unpredictable data accesses.
Proceedings of the 13th European Signal Processing Conference, 2005
Proceedings of the 13th European Signal Processing Conference, 2005
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005
2004
Tech. Sci. Informatiques, 2004
Reed-Solomon behavioral virtual component for communication systems.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
2002
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002
2001
Architectural synthesis of digital signal processing applications dedicated to submicron technologies.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
1999
Architectural Synthesis with Interconnection Cost Control.
Proceedings of the VLSI: Systems on a Chip, 1999
1996
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996
Proceedings of the 1996 European Design and Test Conference, 1996
1994
Proceedings of the Seventh International Conference on VLSI Design, 1994