Taeryeong Kim

According to our database1, Taeryeong Kim authored at least 3 papers between 2022 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
An Energy-Efficient Design of TSV I/O for HBM With a Data Rate up to 10 Gb/s.
IEEE J. Solid State Circuits, November, 2023

A Low-Voltage Area-Efficient TSV I/O for HBM with Data Rate up to 15Gb/s Featuring Overlapped Multiplexing Driver, ISI Compensators and QEC.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2022
A Low Power TSV I/O with Data Rate up to 10 Gb/s for Next Generation HBM.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022


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