Ki-Ryong Kim

Orcid: 0000-0002-2256-3782

According to our database1, Ki-Ryong Kim authored at least 20 papers between 2013 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2023
An Energy-Efficient Design of TSV I/O for HBM With a Data Rate up to 10 Gb/s.
IEEE J. Solid State Circuits, November, 2023

An Offset-Canceled Sense Amplifier for DRAMs With Hidden Offset-Cancellation Time and Boosted Internal-Voltage-Difference.
IEEE Trans. Circuits Syst. II Express Briefs, September, 2023

2022
SRAM Write Assist Circuit Using Cell Supply Voltage Self-Collapse With Bitline Charge Sharing for Near-Threshold Operation.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

A 5 Gb/s Time-Interleaved Voltage-Mode Duobinary Encoding Scheme for 3-D-Stacked IC.
IEEE J. Solid State Circuits, 2022

SRAM Write- and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased With Technology Scaling.
IEEE J. Solid State Circuits, 2022

A Low Power TSV I/O with Data Rate up to 10 Gb/s for Next Generation HBM.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

A 14-nm Low Voltage SRAM with Charge-Recycling and Charge Self-Saving Techniques for Low-Power Applications.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021
A 0.166 pJ/b/pF, 3.5-5 Gb/s TSV I/O Interface With V<sub>OH</sub> Drift Control.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

A 6.9-μm<sup>2</sup> 3.26-ns 31.25-fj Robust Level Shifter With Wide Voltage and Frequency Ranges.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Bitline Charge Sharing Suppressed Bitline and Cell Supply Collapse Assists for Energy-Efficient 6T SRAM.
IEEE Access, 2021

SRAM Write- and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased with Technology Scaling.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

2020
Area- and Energy-Efficient STDP Learning Algorithm for Spiking Neural Network SoC.
IEEE Access, 2020

2018
0.293-mm<sup>2</sup> Fast Transient Response Hysteretic Quasi-V<sup>2</sup> DC-DC Converter With Area-Efficient Time-Domain-Based Controller in 0.35-µm CMOS.
IEEE J. Solid State Circuits, 2018

Triplet-based Spike Timing Dependent Plasticity Circuit Design for three-terminal Spintronic Synapse.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2016
Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Transient Cell Supply Voltage Collapse Write Assist Using Charge Redistribution.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

Thermal and solar energy harvesting boost converter with time-multiplexing MPPT algorithm.
IEICE Electron. Express, 2016

2013
Magnetic Resonance Wireless Power Transmission Using a LLC Resonant Circuit for a Locomotion Robot's Battery Charging.
Proceedings of the Intelligent Robotics and Applications - 6th International Conference, 2013

Bunker Oil C Heating Using Induction Heating.
Proceedings of the Intelligent Robotics and Applications - 6th International Conference, 2013

Research on the MPPT Simulation of Mini Photovoltaic System for the Robotic Vacuum Cleaner Battery Charging.
Proceedings of the Intelligent Robotics and Applications - 6th International Conference, 2013


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