Taeweon Suh

Orcid: 0000-0002-6377-5482

According to our database1, Taeweon Suh authored at least 53 papers between 2004 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 


On csauthors.net:


StarSPA: Stride-Aware Sparsity Compression for Efficient CNN Acceleration.
IEEE Access, 2024

TPU as Cryptographic Accelerator.
CoRR, 2023

Vizard: Passing Over Profiling-Based Detection by Manipulating Performance Counters.
IEEE Access, 2023

Optimization of Microarchitecture and Dataflow for Sparse Tensor CNN Acceleration.
IEEE Access, 2023

Decentralized Translator of Trust: Supporting Heterogeneous TEE for Critical Infrastructure Protection.
Proceedings of the 5th ACM International Symposium on Blockchain and Secure Critical Infrastructure, 2023

Continual Learning With Speculative Backpropagation and Activation History.
IEEE Access, 2022

GhostLeg: Selective Memory Coalescing for Secure GPU Architecture.
IEEE Access, 2022

CacheRewinder: Revoking Speculative Cache Updates Exploiting Write-Back Buffer.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Eavesdropping Vulnerability and Countermeasure in Infrared Communication for IoT Devices.
Sensors, 2021

A Secure and Flexible FPGA-Based Blockchain System for the IIoT.
Computer, 2021

Hardware-Based FLUSH+RELOAD Attack on Armv8 System via ACP.
Proceedings of the International Conference on Information Networking, 2021

DIoTA: Decentralized-Ledger-Based Framework for Data Authenticity Protection in IoT Systems.
IEEE Netw., 2020

Speculative Backpropagation for CNN Parallel Training.
IEEE Access, 2020

Blockchain based End-to-end Tracking System for Distributed IoT Intelligence Application Security Enhancement.
Proceedings of the 19th IEEE International Conference on Trust, 2020

FPGA based Blockchain System for Industrial IoT.
Proceedings of the 19th IEEE International Conference on Trust, 2020

DQN-based OpenCL workload partition for performance optimization.
J. Supercomput., 2019

FPGALedger: FPGA based Decentralized Ledger for Enterprise Applications.
Proceedings of the IEEE International Conference on Blockchain and Cryptocurrency, 2019

SafeDB: Spark Acceleration on FPGA Clouds with Enclaved Data Processing and Bitstream Protection.
Proceedings of the 12th IEEE International Conference on Cloud Computing, 2019

Architectural Protection of Application Privacy against Software and Physical Attacks in Untrusted Cloud Environment.
IEEE Trans. Cloud Comput., 2018

IEEE Des. Test, 2018

FASTEN: An FPGA-Based Secure System for Big Data Processing.
IEEE Des. Test, 2018

Evaluating coherence-exploiting hardware Trojan.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Leveraging Process Variation for Performance and Energy: In the Perspective of Overclocking.
IEEE Trans. Computers, 2014

Mobility-aware balanced scheduling algorithm in mobile Grid based on mobile agent.
Knowl. Eng. Rev., 2014

Estimated Interval-Based Checkpointing (EIC) on Spot Instances in Cloud Computing.
J. Appl. Math., 2014

A Workflow Scheduling Technique Using Genetic Algorithm in Spot Instance-Based Cloud.
KSII Trans. Internet Inf. Syst., 2014

Scalable and leaderless Byzantine consensus in cloud computing environments.
Inf. Syst. Frontiers, 2014

Unstructured deadlock detection technique with scalability and complexity-efficiency in clouds.
Int. J. Commun. Syst., 2014

A scheduling algorithm with dynamic properties in mobile grid.
Frontiers Comput. Sci., 2014

Privacy preserving large scale DNA read-mapping in MapReduce framework using FPGAs.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Unstructured Membership Management for Byzantine Fault Tolerance in Clouds.
Proceedings of the ARCS 2014, 2014

PFC: Privacy Preserving FPGA Cloud - A Case Study of MapReduce.
Proceedings of the 2014 IEEE 7th International Conference on Cloud Computing, Anchorage, AK, USA, June 27, 2014

Performance evaluation of many-core systems: case study with TILEPro64.
IET Comput. Digit. Tech., 2013

Accelerating Histograms of Oriented Gradients descriptor extraction for pedestrian recognition.
Comput. Electr. Eng., 2013

Multi-processor architectural support for protecting virtual machine privacy in untrusted cloud environment.
Proceedings of the Computing Frontiers Conference, 2013

An Unstructured Termination Detection Algorithm Using Gossip in Cloud Computing Environments.
Proceedings of the Architecture of Computing Systems - ARCS 2013, 2013

Pipelined CPU Design With FPGA in Teaching Computer Architecture.
IEEE Trans. Educ., 2012

Using virtual platform in embedded system education.
Comput. Appl. Eng. Educ., 2012

Architectural support of multiple hypervisors over single platform for enhancing cloud computing security.
Proceedings of the Computing Frontiers Conference, CF'12, 2012

Adaptive service scheduling for workflow applications in Service-Oriented Grid.
J. Supercomput., 2010

A Personalized English Vocabulary Learning System Based on Cognitive Abilities Related to Foreign Language Proficiency.
KSII Trans. Internet Inf. Syst., 2010

Group-based Scheduling Algorithm for Fault Tolerance in Mobile Grid.
Proceedings of the Security-Enriched Urban Computing and Smart Grid, 2010

An Effective Job Replication Technique Based on Reliability and Performance in Mobile Grids.
Proceedings of the Advances in Grid and Pervasive Computing, 5th International Conference, 2010

Mobile Grid System Based on Mobile Agent.
Proceedings of the Grid and Distributed Computing, Control and Automation, 2010

A Potential Based Routing Protocol for Mobile Ad Hoc Networks.
Proceedings of the 11th IEEE International Conference on High Performance Computing and Communications, 2009

Balanced Scheduling Algorithm Considering Availability in Mobile Grid.
Proceedings of the Advances in Grid and Pervasive Computing, 4th International Conference, 2009

A Desktop Computer with a Reconfigurable Pentium®.
ACM Trans. Reconfigurable Technol. Syst., 2008

An FPGA Approach to Quantifying Coherence Traffic Efficiency on Multiprocessor Systems.
Proceedings of the FPL 2007, 2007

An FPGA-based Pentium in a complete desktop system.
Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, 2007

Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs.
Proceedings of the 42nd Design Automation Conference, 2005

Integrating Cache Coherence Protocols for Heterogeneous Multiprocessor Systems, Part 2.
IEEE Micro, 2004

Integrating Cache Coherence Protocols for Heterogeneous Multiprocessor Systems, Part 1.
IEEE Micro, 2004

Supporting Cache Coherence in Heterogeneous Multiprocessor Systems.
Proceedings of the 2004 Design, 2004