Dong Hyuk Woo

According to our database1, Dong Hyuk Woo authored at least 21 papers between 2006 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2015
GREEN Cache: Exploiting the Disciplined Memory Model of OpenCL on GPUs.
IEEE Trans. Computers, 2015

Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory).
IEEE Trans. Computers, 2015

2013
Pragmatic Integration of an SRAM Row Cache in Heterogeneous 3-D DRAM Architecture Using TSV.
IEEE Trans. Very Large Scale Integr. Syst., 2013

SIMD divergence optimization through intra-warp compaction.
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

2012

Hybrid DRAM/PRAM-based main memory for single-chip CPU/GPU.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Architectural support of multiple hypervisors over single platform for enhancing cloud computing security.
Proceedings of the Computing Frontiers Conference, CF'12, 2012

Acceleration of bulk memory operations in a heterogeneous multicore architecture.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2011
Security Refresh: Protecting Phase-Change Memory against Malicious Wear Out.
IEEE Micro, 2011

2010
Designing heterogeneous many-core processors to provide high performance under limited chip power budget.
PhD thesis, 2010

Chameleon: Virtualizing idle acceleration cores of a heterogeneous multicore processor for caching and prefetching.
ACM Trans. Archit. Code Optim., 2010

Active Channel Reservation for Coexistence Mechanism (ACROS) for IEEE 802.15.4 and IEEE 802.11.
IEICE Trans. Commun., 2010

SAFER: Stuck-At-Fault Error Recovery for Memories.
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

Security refresh: prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized address mapping.
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

An optimized 3D-stacked memory architecture by exploiting excessive, high-density TSV bandwidth.
Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010

Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

COMPASS: a programmable data prefetcher using idle GPU shaders.
Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, 2010

2009
PROPHET: goal-oriented provisioning for highly tunable multicore processors in cloud computing.
ACM SIGOPS Oper. Syst. Rev., 2009

2008
POD: A 3D-Integrated Broad-Purpose Acceleration Layer.
IEEE Micro, 2008

Extending Amdahl's Law for Energy-Efficient Computing in the Many-Core Era.
Computer, 2008

2006
Reducing energy of virtual cache synonym lookup using bloom filters.
Proceedings of the 2006 International Conference on Compilers, 2006


  Loading...