Joonho Kong
Orcid: 0000-0002-9013-9561
According to our database1,
Joonho Kong
authored at least 39 papers
between 2009 and 2023.
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Bibliography
2023
Linearization Weight Compression and In-Situ Hardware-Based Decompression for Attention-Based Neural Machine Translation.
IEEE Access, 2023
IEEE Access, 2023
2022
Sparse convolutional neural network acceleration with lossless input feature map compression for resource-constrained systems.
IET Comput. Digit. Tech., 2022
Security Issues in Situational Awareness: Adversarial Threats and Mitigation Techniques.
IEEE Secur. Priv., 2022
Row-Wise Product-Based Sparse Matrix Multiplication Hardware Accelerator With Optimal Load Balancing.
IEEE Access, 2022
2021
IEEE Trans. Emerg. Top. Comput., 2021
FogSurv: A Fog-Assisted Architecture for Urban Surveillance Using Artificial Intelligence and Data Fusion.
IEEE Access, 2021
IEEE Access, 2021
Arithmetic Coding-Based 5-Bit Weight Encoding and Hardware Decoder for CNN Inference in Edge Devices.
IEEE Access, 2021
2020
IEEE Trans. Computers, 2020
IEEE Access, 2020
An Integrated Safe and Secure Approach for Authentication and Secret Key Establishment in Automotive Cyber-Physical Systems.
Proceedings of the Intelligent Computing, 2020
2019
Memory streaming acceleration for embedded systems with CPU-accelerator cooperative data processing.
Microprocess. Microsystems, 2019
A Framework for Distributed Deep Neural Network Training with Heterogeneous Computing Platforms.
Proceedings of the 25th IEEE International Conference on Parallel and Distributed Systems, 2019
2018
A Survey on Recent OS-Level Energy Management Techniques for Mobile Processing Units.
IEEE Trans. Parallel Distributed Syst., 2018
3D die-stacked DRAM thermal management via task allocation and core pipeline control.
IEICE Electron. Express, 2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
2017
Towards refresh-optimized EDRAM-based caches with a selective fine-grain round-robin refresh scheme.
Microprocess. Microsystems, 2017
An efficient trade-off between yield and energy for eDRAM caches under process variations.
Microprocess. Microsystems, 2017
IEICE Electron. Express, 2017
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017
2016
IEICE Electron. Express, 2016
2015
An Energy-Efficient Last-Level Cache Architecture for Process Variation-Tolerant 3D Microprocessors.
IEEE Trans. Computers, 2015
Fine-Grained Voltage Boosting for Improving Yield in Near-Threshold Many-Core Processors.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
2014
Processor-Based Strong Physical Unclonable Functions With Aging-Based Response Tuning.
IEEE Trans. Emerg. Top. Comput., 2014
Leveraging Process Variation for Performance and Energy: In the Perspective of Overclocking.
IEEE Trans. Computers, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
2013
ACM Trans. Design Autom. Electr. Syst., 2013
Process variation-tolerant 3D microprocessor design: An efficient architectural solution.
Proceedings of 2013 International Conference on IC Design & Technology, 2013
2012
Fine-Grain Voltage Tuned Cache Architecture for Yield Management Under Process Variations.
IEEE Trans. Very Large Scale Integr. Syst., 2012
IEEE Trans. Consumer Electron., 2012
An online power estimation technique for multi-core smartphones with advanced display components.
Proceedings of the IEEE International Conference on Consumer Electronics, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
2011
2010
IEEE Trans. Dependable Secur. Comput., 2010
2009
Selective wordline voltage boosting for caches to manage yield under process variations.
Proceedings of the 46th Design Automation Conference, 2009