Taiga Takata

According to our database, Taiga Takata authored at least 11 papers between 2005 and 2013.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2013

Efficient Fault Simulation Algorithms for Analyzing Soft Error Propagation in Sequential Circuits.

Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga

IPSJ Trans. Syst. LSI Des. Methodol., 2013

2011

Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure.

Shusuke Yoshimoto, Takuro Amashita, D. Kozuwa, Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Hiroshi Kawaguchi, Masahiko Yoshimoto

Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

A robust algorithm for pessimistic analysis of logic masking effects in combinational circuits.

Taiga Takata, Yusuke Matsunaga

Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

2010

A heuristic algorithm for LUT-based FPGA technology mapping using the lower bound for DAG covering problem (abstract only).

Taiga Takata, Yusuke Matsunaga

Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

2009

Area Recovery under Depth Constraint for Technology Mapping for LUT-based FPGAs.

Taiga Takata, Yusuke Matsunaga

IPSJ Trans. Syst. LSI Des. Methodol., 2009

Efficient Cut Enumeration Heuristics for Depth-Optimum Technology Mapping for LUT-Based FPGAs.

Taiga Takata, Yusuke Matsunaga

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs.

Taiga Takata, Yusuke Matsunaga

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

2008

Area recovery under depth constraint by Cut Substitution for technology mapping for LUT-based FPGAs.

Taiga Takata, Yusuke Matsunaga

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2006

Cell Library Development Methodology for Throughput Enhancement of Character Projection Equipment.

Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki J. Murakami, Katsuya Okumura

IEICE Trans. Electron., 2006

A character size optimization technique for throughput enhancement of character projection lithography.

Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki J. Murakami, Katsuya Okumura

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005

Cell Library Development Methodology for Throughput Enhancement of Electron Beam Direct-Write Lithography Systems.

Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki J. Murakami, Katsuya Okumura

Proceedings of the 2005 International Symposium on System-on-Chip, 2005