Shusuke Yoshimoto
Orcid: 0000-0002-0891-0661
According to our database1,
Shusuke Yoshimoto
authored at least 43 papers
between 2009 and 2022.
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Bibliography
2022
HARU Sleep: A Deep Learning-Based Sleep Scoring System With Wearable Sheet-Type Frontal EEG Sensors.
IEEE Access, 2022
2020
Printable Transparent Microelectrodes toward Mechanically and Visually Imperceptible Electronics.
Adv. Intell. Syst., 2020
2019
A 28-nm FD-SOI 8T Dual-Port SRAM for Low-Energy Image Processor With Selective Sourceline Drive Scheme.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Proceedings of the 13th International Symposium on Medical Information and Communication Technology, 2019
2017
IEICE Electron. Express, 2017
Flexible organic TFT bio-signal amplifier using reliable chip component assembly process with conductive adhesive.
Proceedings of the 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2017
Flexible sensor sheet for real-time pressure monitoring in artificial knee joint during total knee arthroplasty.
Proceedings of the 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2017
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017
2016
A Counter-based Read Circuit Tolerant to Process Variation for 0.4-V Operating STT-MRAM.
IPSJ Trans. Syst. LSI Des. Methodol., 2016
A 28-nm 484-fJ/writecycle 650-fJ/readcycle 8T Three-Port FD-SOI SRAM for Image Processor.
IEICE Trans. Electron., 2016
An low-energy 8T dual-port SRAM for image processor with selective sourceline drive scheme in 28-nm FD-SOI process technology.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
Wireless EEG patch sensor on forehead using on-demand stretchable electrode sheet and electrode-tissue impedance scanner.
Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016
Implantable wireless 64-channel system with flexible ECoG electrode and optogenetics probe.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016
2015
IEEE Trans. Biomed. Circuits Syst., 2015
A low power 6T-4C non-volatile memory using charge sharing and non-precharge techniques.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
A 298-fJ/writecycle 650-fJ/readcycle 8T three-port SRAM in 28-nm FD-SOI process technology for image processor.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
A 6.14µA normally-off ECG-SoC with noise tolerant heart rate extractor for wearable healthcare systems.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014
2013
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
A 40-nm 8T SRAM with selective source line control of read bitlines and address preset structure.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
A physical unclonable function chip exploiting load transistors' variation in SRAM bitcells.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
IEICE Trans. Electron., 2012
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure.
IEICE Trans. Electron., 2012
A 128-bit Chip Identification Generating Scheme Exploiting Load Transistors' Variation in SRAM Bitcells.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
A 0.15-µm FD-SOI Substrate Bias Control SRAM with Inter-Die Variability Compensation Scheme.
IEICE Trans. Electron., 2012
IEICE Electron. Express, 2012
IEICE Electron. Express, 2012
A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012
2011
7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011
Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011
A 128-bit chip identification generating scheme exploiting SRAM bitcells with failure rate of 4.45 × 10<sup>-19</sup>.
Proceedings of the 37th European Solid-State Circuits Conference, 2011
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
2010
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
2009
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009