Kazuaki J. Murakami
Affiliations:- Team Aibod, Fukuoka, Japan
- Kyushu University, Graduate School of Information Science and Electrical Engineering, Fukuoka, Japan
According to our database1,
Kazuaki J. Murakami
authored at least 104 papers
between 1988 and 2019.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
On csauthors.net:
Bibliography
2019
2018
Multim. Tools Appl., 2018
Proceedings of the 9th International Conference on Awareness Science and Technology, 2018
2017
Comput. Electr. Eng., 2017
2016
Guide Automatic Vectorization by means of Machine Learning: A Case Study of Tensor Contraction Kernels.
IEICE Trans. Inf. Syst., 2016
2015
J. Mobile Multimedia, 2015
Int. J. Big Data Intell., 2015
Proceedings of the 8th International Symposium on Visual Information Communication and Interaction, 2015
Proceedings of the Information and Communication Technology, 2015
Proceedings of the Third International Symposium on Computing and Networking, 2015
2014
IEICE Trans. Inf. Syst., 2014
IEICE Trans. Electron., 2014
Proceedings of the 2014 Spring Simulation Multiconference, 2014
Proceedings of the ISDOC 2014, 2014
A Design Methodology for Performance Maintenance of 3D Network-on-Chip with Multiplexed Through-Silicon Vias.
Proceedings of the 3rd International Workshop on Many-core Embedded Systems (MES'2015) held on June 13, 2014
Proceedings of the IIAI 3rd International Conference on Advanced Applied Informatics, 2014
Proceedings of the IIAI 3rd International Conference on Advanced Applied Informatics, 2014
2013
Proceedings of the International Conference on Supercomputing, 2013
Proceedings of the International Conference on Computational Science, 2013
Proceedings of the 2013 IEEE International Conference on Green Computing and Communications (GreenCom) and IEEE Internet of Things (iThings) and IEEE Cyber, 2013
Early stage power management for 3D FPGAs considering hierarchical routing resources.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013
2012
Improving performance and energy efficiency of embedded processors via post-fabrication instruction set customization.
J. Supercomput., 2012
SIGARCH Comput. Archit. News, 2012
IEICE Trans. Inf. Syst., 2012
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012
Proceedings of the 2012 Workshop on Power-Aware Computing Systems, HotPower'12, 2012
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
2011
SIGARCH Comput. Archit. News, 2011
A design scheme for a reconfigurable accelerator implemented by single-flux quantum circuits.
J. Syst. Archit., 2011
IEICE Trans. Inf. Syst., 2011
Proceedings of the International Conference on Electrical Engineering and Informatics, 2011
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011
Routing architecture and algorithms for a superconductivity circuits-based computing hardware.
Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011
A thermal-aware mapping algorithm for reducing peak temperature of an accelerator deployed in a 3D stack.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011
Performance evaluation of 3D stacked multi-core processors with temperature consideration.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011
2010
Mapping scientific applications on a large-scale data-path accelerator implemented by single-flux quantum (SFQ) circuits.
Proceedings of the Design, Automation and Test in Europe, 2010
2009
Identifying Processor Bottlenecks in Virtual Machine Based Execution of Java Bytecode.
IEICE Trans. Electron., 2009
IEICE Trans. Electron., 2009
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
Accelerating Cryptographic Applications Using Dynamically Reconfigurable Functional Units.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009
Performance balancing: software-based on-chip memory management for effective CMP executions.
Proceedings of the 10th workshop on MEmory performance, 2009
Proceedings of the Second International Joint Conference on Computational Sciences and Optimization, 2009
A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
Proceedings of the Architecture of Computing Systems, 2009
2008
J. Supercomput., 2008
Proposal of a Desk-Side Supercomputer with Reconfigurable Data-Paths Using Rapid Single-Flux-Quantum Circuits.
IEICE Trans. Electron., 2008
Character Projection Mask Set Optimization for Enhancing Throughput of MCC Projection Systems.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
IEICE Trans. Electron., 2008
A Reconfigurable Functional Unit with Conditional Execution for Multi-Exit Custom Instructions.
IEICE Trans. Electron., 2008
IEICE Trans. Electron., 2008
IEICE Trans. Commun., 2008
Performance prediction of large-scale parallell system and application using macro-level simulation.
Proceedings of the ACM/IEEE Conference on High Performance Computing, 2008
Improving Energy Efficiency of Configurable Caches via Temperature-Aware Configuration Selection.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
Enhancing energy efficiency of processor-based embedded systems through post-fabrication ISA extension.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
Proceedings of the 13th Asia-Pacific Computer Systems Architecture Conference, 2008
2007
Technology Mapping Technique for Increasing Throughput of Character Projection Lithography.
IEICE Trans. Electron., 2007
Architectural-Level Soft-Error Modeling for Estimating Reliability of Computer Systems.
IEICE Trans. Electron., 2007
IEICE Trans. Electron., 2007
Improving Performance and Energy Saving in a Reconfigurable Processor via Accelerating Control Data Flow Graphs.
IEICE Trans. Inf. Syst., 2007
Performance Analysis and Linear Optimization Modeling of All-to-all Collective Communication Algorithms.
Proceedings of the 19th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2007), 2007
Proceedings of the Recent Advances in Parallel Virtual Machine and Message Passing Interface, 14th European PVM/MPI User's Group Meeting, Paris, France, September 30, 2007
Proceedings of the Embedded Software and Systems, [Third] International Conference, 2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Interactive presentation: Generating and executing multi-exit custom instructions for an adaptive extensible processor.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
The Effect of Nanometer-Scale Technologies on the Cache Size Selection for Low Energy Embedded Systems.
Proceedings of the 2007 International Conference on Embedded Systems & Applications, 2007
2006
Cell Library Development Methodology for Throughput Enhancement of Character Projection Equipment.
IEICE Trans. Electron., 2006
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006
Preliminary performance evaluation of an adaptive dynamic extensible processor for embedded applications.
Proceedings of the 2006 ACM Symposium on Applied Computing (SAC), 2006
A character size optimization technique for throughput enhancement of character projection lithography.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Reducing reconfiguration time of reconfigurable computing systems in integrated temporal partitioning and physical design framework.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006
Proceedings of the High Performance Computing, 2006
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006
Custom Instruction Generation Using Temporal Partitioning Techniques for a Reconfigurable Functional Unit.
Proceedings of the Embedded and Ubiquitous Computing, International Conference, 2006
GifT: A Gravity-Directed and Life-Time Based Algorithm for Temporal Partitioning of Data Flow Graphs.
Proceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2006
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
An Integrated Temporal Partitioning and Mapping Framework for Handling Custom Instructions on a Reconfigurable Functional Unit.
Proceedings of the Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, 2006
2005
Quantitative Evaluation of State-Preserving Leakage Reduction Algorithm for L1 Data Caches.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
Cell Library Development Methodology for Throughput Enhancement of Electron Beam Direct-Write Lithography Systems.
Proceedings of the 2005 International Symposium on System-on-Chip, 2005
2004
Practical Test Architecture Optimization for System-on-a-Chip under Floorplanning Constraints.
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004
Proceedings of the 2004 International Symposium on System-on-Chip, 2004
2003
Instruction Encoding for Reducing Power Consumption of I-ROMs Based on Execution Locality.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003
2002
Dynamic Tag-Check Omission: A Low Power Instruction Cache Architecture Exploiting Execution Footprints.
Proceedings of the Power-Aware Computer Systems, Second International Workshop, 2002
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002
2001
Development of PPRAM-link interface (PLIF) IP core for high-speed inter-SoC communication.
Proceedings of ASP-DAC 2001, 2001
2000
Performance/Energy Efficiency of Variable Line-Size Caches for Intelligent Memory Systems.
Proceedings of the Intelligent Memory Systems, Second International Workshop, 2000
1999
MOE: A Special-Purpose Parallel Computer for High-Speed, Large-Scale Molecular Orbital Calculation.
Proceedings of the ACM/IEEE Conference on Supercomputing, 1999
Way-predicting set-associative cache for high performance and low energy consumption.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999
Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs.
Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, 1999
1998
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998
1993
Proceedings of the 7th international conference on Supercomputing, 1993
1992
Benchmarking a vector-processor prototype based on multithreaded streaming/FIFO vector (MSFV) architecture.
Proceedings of the 6th international conference on Supercomputing, 1992
1991
DSNS (dynamically-hazard-resolved statically-code-scheduled, nonuniform superscalar): yet another superscalar processor architecture.
SIGARCH Comput. Archit. News, 1991
Toward advanced parallel processing: exploiting parallelism at task and instruction levels.
IEEE Micro, 1991
1989
SIMP (Single Instruction stream/Multiple Instruction Pipelining): A Novel High-Speed Single-Processor Architecture.
Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, 1989
The Kyushu University Reconfigurable Parallel Processor - Design Philosophy and Architecture.
Proceedings of the Information Processing 89, Proceedings of the IFIP 11th World Computer Congress, San Francisco, USA, August 28, 1989
The Kyushu University reconfigurable parallel processor: design of memory and intercommunicaiton architectures.
Proceedings of the 3rd international conference on Supercomputing, 1989
1988
SIGARCH Comput. Archit. News, 1988