Masayoshi Yoshimura
According to our database1,
Masayoshi Yoshimura
authored at least 34 papers
between 2001 and 2024.
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Bibliography
2024
CRLock: A SAT and FALL Attacks Resistant Logic Locking Method for Controller at Register Transfer Level.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2024
2023
An Evaluation of Estimated Field Random Testability for Data Paths at Register Transfer Level Using Status Signal Sequences Based on k-Consecutive State Transitions for Field Testing.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023
A Block Partitioning Method for Region Exhaustive Test to Reduce the Number of Test Patterns and Improve Gate Exhaustive Fault Coverage.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023
An Evaluation of a Testability Measure for State Assignment to Estimate Transition Fault Coverage for Controllers.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023
2022
CRLock: A SAT and FALL Attacks Resistant Logic Locking Method at Register Transfer Level.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022
2020
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020
A Multiple Target Test Generation Method for Gate-Exhaustive Faults to Reduce the Number of Test Patterns Using Partial MaxSAT.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020
2019
A Controller Augmentation Method to Improve Transition Fault Coverage for RTL Data-Paths.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019
2018
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
A Test Register Assignment Method Based on Controller Augmentation to Reduce the Number of Test Patterns.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
A Sequentially Untestable Fault Identification Method Based on n-Bit State Cube Justification.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
2017
A Don't Care Filling Method for Low Capture Power based on Correlation of FF Transitions Using SAT.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
Proceedings of the 22nd IEEE Pacific Rim International Symposium on Dependable Computing, 2017
Controller augmentation and test point insertion at RTL for concurrent operational unit testing.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
2015
A Don't Care Filling Method to Reduce Capture Power Based on Correlation of FF Transitions.
Proceedings of the 24th IEEE Asian Test Symposium, 2015
2013
Efficient Fault Simulation Algorithms for Analyzing Soft Error Propagation in Sequential Circuits.
IPSJ Trans. Syst. LSI Des. Methodol., 2013
A Test Compaction Oriented Don't Care Identification Method Based on X-bit Distribution.
IEICE Trans. Inf. Syst., 2013
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013
2012
An Exact Estimation Algorithm of Error Propagation Probability for Sequential Circuits.
IPSJ Trans. Syst. LSI Des. Methodol., 2012
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012
2011
Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011
2010
Evaluation of transition untestable faults using a multi-cycle capture test generation method.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010
2006
Proceedings of the 15th Asian Test Symposium, 2006
2005
Implementation of Multiobjective Optimization Procedures at the Product Design Planning Stage.
Proceedings of the System Modeling and Optimization, 2005
2004
Proceedings of the 4th IEEE International Symposium on BioInformatics and BioEngineering (BIBE 2004), 2004
2002
Collaborative optimization for product design and manufacturing.
Proceedings of the CAD 2002: Corporate Engineering Research, Dresden, March 4-5, 2002, 2002
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002
2001
Design for testability strategies using full/partial scan designs and test point insertions to reduce test application times.
Proceedings of ASP-DAC 2001, 2001