Jianxun Yang

Orcid: 0000-0001-9905-0961

According to our database1, Jianxun Yang authored at least 11 papers between 2017 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
Reconstruction of the S-Wave Velocity via Mixture Density Networks With a New Rayleigh Wave Dispersion Function.
IEEE Trans. Geosci. Remote. Sens., 2022

GQNA: Generic Quantized DNN Accelerator With Weight-Repetition-Aware Activation Aggregating.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Modeling the pile settlement using the Integrated Radial Basis Function (RBF) neural network by Novel Optimization algorithms: HRBF-AOA and HRBF-BBO.
J. Intell. Fuzzy Syst., 2022

2021
TIMAQ: A Time-Domain Computing-in-Memory-Based Processor Using Predictable Decomposed Convolution for Arbitrary Quantized DNNs.
IEEE J. Solid State Circuits, 2021

A new mathematical model for dispersion of Rayleigh wave and a machine learning based inversion solver.
CoRR, 2021

FuseKNA: Fused Kernel Convolution based Accelerator for Deep Neural Networks.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

2020
A Time-Domain Computing-in-Memory based Processor using Predictable Decomposed Convolution for Arbitrary Quantized DNNs.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020

2019
An Energy-Efficient Reconfigurable Processor for Binary-and Ternary-Weight Neural Networks With Flexible Data Bit Width.
IEEE J. Solid State Circuits, 2019

An Energy-Efficient Architecture for Accelerating Inference of Memory-Augmented Neural Networks.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019

2018
An Ultra-High Energy-Efficient Reconfigurable Processor for Deep Neural Networks with Binary/Ternary Weights in 28NM CMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

2017
A two-stage variation-aware task mapping scheme for fault-tolerant multi-core Network-on-Chips.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017


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