Takeomi Tamesada

According to our database, Takeomi Tamesada authored at least 30 papers between 1980 and 2006.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2006

Current Testable Design of Resistor String DACs.

Masaki Hashizume, Tomomi Nishida, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura

Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

2005

Electric field for detecting open leads in CMOS logic circuits by supply current testing.

Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004

A test circuit for pin shorts generating oscillation in CMOS logic circuits.

Masahiro Ichimiya, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada

Syst. Comput. Jpn., 2004

Test Sequence Generation for Test Time Reduction of IDDQ Testing.

Hiroyuki Yotsuyanagi, Masaki Hashizume, Takeomi Tamesada

IEICE Trans. Inf. Syst., 2004

Identification and Frequency Estimation of Feedback Bridging Faults Generating Logical Oscillation in CMOS Circuits.

Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada

IEICE Trans. Inf. Syst., 2004

Practical Fault Coverage of Supply Current Tests for Bipolar ICs.

Isao Tsukimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada

Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

CMOS Open Fault Detection by Appearance Time of Switching Supply Current.

Masaki Hashizume, Tetsuo Akita, Hiroyuki Yotsuyanagi, Takeomi Tamesada

Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

A Power Supply Circuit Recycling Charge in Adiabatic Dynamic CMOS Logic Circuits.

Daisuke Ezaki, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada

Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

I_DDQ Test Method Based on Wavelet Transformation for Noisy Current Measurement Environment.

Masaki Hashizume, Daisuke Yoneda, Hiroyuki Yotsuyanagi, Tetsuo Tada, Takeshi Koyama, Ikuro Morita, Takeomi Tamesada

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003

A BIST Circuit for IDDQ Tests.

Masaki Hashizume, Teppei Takeda, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura, Kozo Kinoshita

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002

Random Pattern Testability of the Open Defect Detection Method using Application of Time-variable Electric Field.

Hiroyuki Yotsuyanagi, Masaki Hashizume, Taisuke Iwakiri, Masahiro Ichimiya, Takeomi Tamesada

Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

Power Supply Circuit for High Speed Operation of Adiabatic Dynamic CMOS Logic Circuits.

Masaki Hashizume, Masashi Sato, Hiroyuki Yotsuyanagi, Takeomi Tamesada

Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

Test Time Reduction for I DDQ Testing by Arranging Test Vectors.

Hiroyuki Yotsuyanagi, Masaki Hashizume, Takeomi Tamesada

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001

Test Pattern for Supply Current Test of Open Defects by Applying Time-Variable Electric Field.

Hiroyuki Yotsuyanagi, Masaki Hashizume, Taisuke Iwakiri, Masahiro Ichimiya, Takeomi Tamesada

Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

CMOS open defect detection by supply current test.

Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Sequential Redundancy Removal Using Test Generation and Multiple Unreachable States.

Hiroyuki Yotsuyanagi, Shinsuke Hata, Masaki Hashizume, Takeomi Tamesada

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

CMOS Open Defect Detection Based on Supply Current in Time-Variable Electric Field and Supply Voltage Application.

Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000

Testability Analysis of IDDQ Testing with Large Threshold Value.

Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Masashi Takeda

Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000

High speed IDDQ test and its testability for process variation.

Masaki Hashizume, Hiroyuki Yotsuyanagi, Masahiro Ichimiya, Takeomi Tamesada, Masashi Takeda

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999

Identification of Feedback Bridging Faults with Oscillation.

Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1998

A High-Speed IDDQ Sensor for Low-Voltage ICs.

Masaki Hashizume, Yukiya Miura, Masahiro Ichimiya, Takeomi Tamesada, Kozo Kinoshita

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997

Supply Current Test for Unit-to-unit Variations of Electrical Characteristics in Gates.

Masaki Hashizume, Toshimasa Kuchii, Takeomi Tamesada

Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1996

Algorithmic Test Generation for Supply Current Testing of TTL Combinational Circuits.

Toshimasa Kuchii, Masaki Hashizume, Takeomi Tamesada

Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

1994

A Maximum Clique Derivation Algorithm for Simplification of Incompletely Specified Machines.

Masaki Hashizume, Takeomi Tamesada, Akio Sakamoto

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1990

A parameter adjustment method for analog circuits based on convex fuzzy decision using constraints of satisfactory level.

Masaki Hashizume, Takeomi Tamesada, Koji Nii

Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

1989

High-speed multioperand addition and subtraction using a p-ary representation with necessary and minimum redundancy.

Takeomi Tamesada

Syst. Comput. Jpn., 1989

Evaluation of a retrieval system using content addressable memory.

Masaki Hashizume, Hirosuke Yamamoto, Takeomi Tamesada, Toshiaki Hanibuti

Syst. Comput. Jpn., 1989

1988

High-speed addition and subtraction using a minimum redundant p-ary representation.

Takeomi Tamesada

Syst. Comput. Jpn., 1988

Fault Detection of Combinational Circuits Based on Supply Current.

Masaki Hashizume, Takeomi Tamesada, Kazuhiro Yamada, Masaaki Kawakami

Proceedings of the Proceedings International Test Conference 1988, 1988

1980

Sequential Machines Having Quasi-Stable States.

Takeomi Tamesada

IEEE Trans. Computers, 1980