Masaki Hashizume

Zhi-Jia Liu

Proceedings of the IEEE 31st Asian Test Symposium, 2022

2020

Fault-Aware Dependability Enhancement Techniques for Flash Memories.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2020

2019

On Delay Measurement Under Delay Variations in Boundary Scan Circuit with Embedded TDC.

[BibT_eX]

[DOI]

Shuya Kikuchi

Proceedings of the IEEE International Test Conference in Asia, 2019

Electrical Field Test Method of Resistive Open Defects between Dies by Quiescent Currents through Embedded Diodes.

[BibT_eX]

[DOI]

Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

On Delay Elements in Boundary Scan Cells for Delay Testing of 3D IC Interconnection.

[BibT_eX]

[DOI]

Toshiaki Satoh

Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

2018

A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2018

Fault Leveling Techniques for Yield and Reliability Enhancement of NAND Flash Memories.

[BibT_eX]

[DOI]

Shang-Xiu Zhong

J. Electron. Test., 2018

Address Remapping Techniques for Enhancing Fabrication Yield of Embedded Memories.

[BibT_eX]

[DOI]

J. Electron. Test., 2018

A Sequentially Untestable Fault Identification Method Based on n-Bit State Cube Justification.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Test Time Reduction on Testing Delay Faults in 3D ICs Using Boundary Scan Design.

[BibT_eX]

[DOI]

Satoshi Hirai

Proceedings of the 27th IEEE Asian Test Symposium, 2018

2017

Discrimination of a Resistive Open Using Anomaly Detection of Delay Variation Induced by Transitions on Adjacent Lines.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

A defect level monitor of resistive open defect at interconnects in 3D ICs by injected charge volume.

[BibT_eX]

[DOI]

Proceedings of the 17th International Symposium on Communications and Information Technologies, 2017

On selection of adjacent lines in test pattern generation for delay faults considering crosstalk effects.

[BibT_eX]

[DOI]

Proceedings of the 17th International Symposium on Communications and Information Technologies, 2017

A defective level monitor of open defects in 3D ICs with a comparator of offset cancellation type.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

Fault-Aware Page Address Remapping Techniques for Enhancing Yield and Reliability of Flash Memories.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE Asian Test Symposium, 2017

Open Defect Detection with a Built-in Test Circuit by IDDT Appearance Time in CMOS ICs.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016

Enhanced Built-In Self-Repair Techniques for Improving Fabrication Yield and Reliability of Embedded Memories.

[BibT_eX]

[DOI]

Cheng-Ju Tsai

IEEE Trans. Very Large Scale Integr. Syst., 2016

A Built-in Test Circuit for Electrical Interconnect Testing of Open Defects in Assembled PCBs.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2016

Adaptive ECC Techniques for Yield and Reliability Enhancement of Flash Memories.

[BibT_eX]

[DOI]

Shang-Xiu Zhong

Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015

Address Scrambling and Data Inversion Techniques for Yield Enhancement of NROM-Based ROMs.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2015

Hybrid scrambling technique for increasing the fabrication yield of NROM-Based ROMs.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design, Automation and Test, 2015

Electrically testable CMOS image pixel circuit.

[BibT_eX]

[DOI]

Shingo Saijo

Hiroyuki Yotsuyanng

Proceedings of the European Conference on Circuit Theory and Design, 2015

Integration of Hard Repair Techniques with ECC for Enhancing Fabrication Yield and Reliability of Embedded Memories.

[BibT_eX]

[DOI]

Cheng-Ju Tsai

Proceedings of the 24th IEEE Asian Test Symposium, 2015

An enhanced built-in self-repair technique for yield and reliability improvement of embedded memories.

[BibT_eX]

[DOI]

Hao-Wei Lin

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

On TSV array defect detection method using two ring-oscillators considering signal transitions at adjacent TSVs.

[BibT_eX]

[DOI]

Akihiro Fujiwara

Proceedings of the 2015 International 3D Systems Integration Conference, 2015

Electrical interconnect test method of 3D ICs by injected charge volume.

[BibT_eX]

[DOI]

Proceedings of the 2015 International 3D Systems Integration Conference, 2015

Electrical interconnect test of 3D ICs made of dies without ESD protection circuits with a built-in test circuit.

[BibT_eX]

[DOI]

Proceedings of the 2015 International 3D Systems Integration Conference, 2015

2014

Efficient test length reduction techniques for interposer-based 2.5D ICs.

[BibT_eX]

[DOI]

Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

Built-In Scrambling Analysis for Yield Enhancement of Embedded Memories.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

A built-in supply current test circuit for electrical interconnect tests of 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 2014 International 3D Systems Integration Conference, 2014

2013

On Detecting Delay Faults Using Time-to-Digital Converter Embedded in Boundary Scan.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2013

SAT-Based Test Generation for Open Faults Using Fault Excitation Caused by Effect of Adjacent Lines.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

An Efficient Test and Repair Flow for Yield Enhancement of One-Time-Programming NROM-Based ROMs.

[BibT_eX]

[DOI]

Tsu-Lin Li

IEICE Trans. Inf. Syst., 2013

Diagnosing Resistive Open Faults Using Small Delay Fault Simulation.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asian Test Symposium, 2013

Fault Scrambling Techniques for Yield Enhancement of Embedded Memories.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asian Test Symposium, 2013

Testable Design for Electrical Testing of Open Defects at Interconnects in 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asian Test Symposium, 2013

2011

A supply current testable register string DAC of decoder type.

[BibT_eX]

[DOI]

Proceedings of the 11th International Symposium on Communications and Information Technologies, 2011

A Boundary Scan Circuit with Time-to-Digital Converter for Delay Testing.

[BibT_eX]

[DOI]

Hiroyuki Makimoto

Proceedings of the 20th IEEE Asian Test Symposium, 2011

A built-in test circuit for open defects at interconnects between dies in 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

Supply current testing of open defects at interconnects in 3D Ics with IEEE 1149.1 architecture.

[BibT_eX]

[DOI]

Tomoaki Konishi

Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2010

Scan Chain Ordering to Reduce Test Data for BIST-Aided Scan Test Using Compatible Scan Flip-Flops.

[BibT_eX]

[DOI]

Masayuki Yamamoto

IEICE Trans. Inf. Syst., 2010

Current-based testable design of level shifters in liquid crystal display drivers.

[BibT_eX]

[DOI]

Proceedings of the 15th European Test Symposium, 2010

Test Data Reduction for BIST-Aided Scan Test Using Compatible Flip-Flops and Shifting Inverter Code.

[BibT_eX]

[DOI]

Masashi Ishikawa

Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009

Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

A Novel Approach for Improving the Quality of Open Fault Diagnosis.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

New Class of Tests for Open Faults with Considering Adjacent Lines.

[BibT_eX]

[DOI]

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2007

Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

Clues for Modeling and Diagnosing Open Faults with Considering Adjacent Lines.

[BibT_eX]

[DOI]

Proceedings of the 16th Asian Test Symposium, 2007

Current Testable Design of Resistor String DACs.

[BibT_eX]

[DOI]

Proceedings of the 16th Asian Test Symposium, 2007

2006

Current Testable Design of Resistor String DACs.

[BibT_eX]

[DOI]

Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

A BIC Sensor Capable of Adjusting IDDQ Limit in Tests.

[BibT_eX]

[DOI]

Proceedings of the 15th Asian Test Symposium, 2006

2005

Reducing Scan Shifts Using Configurations of Compatible and Folding Scan Trees.

[BibT_eX]

[DOI]

J. Electron. Test., 2005

Electric field for detecting open leads in CMOS logic circuits by supply current testing.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004

A test circuit for pin shorts generating oscillation in CMOS logic circuits.

[BibT_eX]

[DOI]

Syst. Comput. Jpn., 2004

Test Sequence Generation for Test Time Reduction of IDDQ Testing.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2004

Identification and Frequency Estimation of Feedback Bridging Faults Generating Logical Oscillation in CMOS Circuits.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2004

On Configuring Scan Trees to Reduce Scan Shifts based on a Circuit Structure.

[BibT_eX]

[DOI]

Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

Practical Fault Coverage of Supply Current Tests for Bipolar ICs.

[BibT_eX]

[DOI]

Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

CMOS Open Fault Detection by Appearance Time of Switching Supply Current.

[BibT_eX]

[DOI]

Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

A Power Supply Circuit Recycling Charge in Adiabatic Dynamic CMOS Logic Circuits.

[BibT_eX]

[DOI]

Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

I_DDQ Test Method Based on Wavelet Transformation for Noisy Current Measurement Environment.

[BibT_eX]

[DOI]

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003

Reducing Scan Shifts Using Folding Scan Trees.

[BibT_eX]

[DOI]

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

A BIST Circuit for IDDQ Tests.

[BibT_eX]

[DOI]

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002

Random Pattern Testability of the Open Defect Detection Method using Application of Time-variable Electric Field.

[BibT_eX]

[DOI]

Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

Power Supply Circuit for High Speed Operation of Adiabatic Dynamic CMOS Logic Circuits.

[BibT_eX]

[DOI]

Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

Test Time Reduction for I DDQ Testing by Arranging Test Vectors.

[BibT_eX]

[DOI]

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001

Test Pattern for Supply Current Test of Open Defects by Applying Time-Variable Electric Field.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

CMOS open defect detection by supply current test.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Sequential Redundancy Removal Using Test Generation and Multiple Unreachable States.

[BibT_eX]

[DOI]

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

IDDQ Sensing Technique for High Speed IDDQ Testing.

[BibT_eX]

[DOI]

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

CMOS Open Defect Detection Based on Supply Current in Time-Variable Electric Field and Supply Voltage Application.

[BibT_eX]

[DOI]

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000

Testability Analysis of IDDQ Testing with Large Threshold Value.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000

High speed IDDQ test and its testability for process variation.

[BibT_eX]

[DOI]

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999

Identification of Feedback Bridging Faults with Oscillation.

[BibT_eX]

[DOI]

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1998

A High-Speed IDDQ Sensor for Low-Voltage ICs.

[BibT_eX]

[DOI]

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997

Supply Current Test for Unit-to-unit Variations of Electrical Characteristics in Gates.

[BibT_eX]

[DOI]

Toshimasa Kuchii

Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1996

Algorithmic Test Generation for Supply Current Testing of TTL Combinational Circuits.

[BibT_eX]

[DOI]

Toshimasa Kuchii

Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

1994

A Maximum Clique Derivation Algorithm for Simplification of Incompletely Specified Machines.

[BibT_eX]

[DOI]

Akio Sakamoto

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1991

Fault detection of ttl combinational circuits based on supply current.

[BibT_eX]

[DOI]

Takeorai Tamesada

Syst. Comput. Jpn., 1991

1990

A parameter adjustment method for analog circuits based on convex fuzzy decision using constraints of satisfactory level.

[BibT_eX]

[DOI]