Takuji Okamoto

According to our database1, Takuji Okamoto authored at least 19 papers between 1983 and 2007.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2007
Detection of CMOS Open Node Defects by Frequency Analysis.
IEICE Trans. Inf. Syst., 2007

2005
Superconductive logic circuits constructed by the use of two thresholds of SQUID.
Syst. Comput. Jpn., 2005

2004
Model analysis of coronary hemodynamics incorporating autoregulation.
Syst. Comput. Jpn., 2004

CMOS Floating Gate Defect Detection Using Supply Current Test with DC Power Supply Superposed by AC Component.
IEICE Trans. Inf. Syst., 2004

2003
Improvement of Detectability for CMOS Floating Gate Defects in Supply Current Test.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002
CMOS Floating Gate Defect Detection Using I DDQ Test with DC Power Supply.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001
A dynamic traffic sharing with minimal administration on multihomed networks.
Proceedings of the IEEE International Conference on Communications, 2001

Synthesis of four-phase asynchronous control circuits from pipeline dependency graphs.
Proceedings of ASP-DAC 2001, 2001

2000
Systematic reducing of metastable operations in CMOS D flip-flops.
Syst. Comput. Jpn., 2000

A method of affine transformation for rectangular video image.
Syst. Comput. Jpn., 2000

1997
Testing for the programming circuit of LUT-based FPGAs.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1996
A method of shortening metastable operation duration time by the use of feedback.
Syst. Comput. Jpn., 1996

Timing verification of asynchronous sequential circuits with specifications - A method of reducing state transitions to be verified in detail.
Syst. Comput. Jpn., 1996

Realization of multiwindow system with high-speed operations of nonrectangular windows.
Syst. Comput. Jpn., 1996

A Test Methodology for Interconnect Structures of LUT-based FPGAs.
Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

1995
The Number of Elements in Minimum Test Set for Locally Exhaustive Testing of Combinational Circuits with Five Outputs.
IEICE Trans. Inf. Syst., 1995

Universal test complexity of field-programmable gate arrays.
Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

1991
Decentralized priority encoder and its applications.
Syst. Comput. Jpn., 1991

1983
Design of High-Level Test Language for Digital LSI.
Proceedings of the Proceedings International Test Conference 1983, 1983


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