Takuya Nakaike

According to our database1, Takuya Nakaike authored at least 16 papers between 1999 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
Hyperledger Fabric Performance Characterization and Optimization Using GoLevelDB Benchmark.
Proceedings of the IEEE International Conference on Blockchain and Cryptocurrency, 2020

2019
Profile-based Detection of Layered Bottlenecks.
Proceedings of the 2019 ACM/SPEC International Conference on Performance Engineering, 2019

2016
Workload characterization for microservices.
Proceedings of the 2016 IEEE International Symposium on Workload Characterization, 2016

2015
Transactional memory support in the IBM POWER8 processor.
IBM J. Res. Dev., 2015

Quantitative comparison of hardware transactional memory for Blue Gene/Q, zEnterprise EC12, Intel Core, and POWER8.
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

2014
Thread-level speculation on off-the-shelf hardware transactional memory.
Proceedings of the 2014 IEEE International Symposium on Workload Characterization, 2014

Characterization of call-graph profiles in Java workloads.
Proceedings of the 2014 IEEE International Symposium on Workload Characterization, 2014

2013
Do C and Java programs scale differently on Hardware Transactional Memory?
Proceedings of the IEEE International Symposium on Workload Characterization, 2013

2010
Lock elision for read-only critical sections in Java.
Proceedings of the 2010 ACM SIGPLAN Conference on Programming Language Design and Implementation, 2010

Real Java applications in software transactional memory.
Proceedings of the 2010 IEEE International Symposium on Workload Characterization, 2010

Coloring-based coalescing for graph coloring register allocation.
Proceedings of the CGO 2010, 2010

2009
Compiler and runtime techniques for software transactional memory optimization.
Concurr. Comput. Pract. Exp., 2009

Reducing Rollbacks of Transactional Memory Using Ordered Shared Locks.
Proceedings of the Euro-Par 2009 Parallel Processing, 2009

2006
Profile-based global live-range splitting.
Proceedings of the ACM SIGPLAN 2006 Conference on Programming Language Design and Implementation, 2006

2004
JSP Splitting for Improving Execution Performance.
Proceedings of the 2004 Symposium on Applications and the Internet (SAINT 2004), 2004

1999
A scheduling method for instruction-level parallel processing of vectorand scalar instructions.
Systems and Computers in Japan, 1999


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